Since the publication of the first edition of this book in 1996, CMOS manufacturing technology has continued its breathtaking pace, scaling to ever-smaller dimensions. Minimum feature sizes are now reaching the 100-rim realm. Circuits are becoming more complex, challenging the productivity of the designer, while the plunge into the deep-submicron space causes devices to behave differently and brings to the forefront a number of new issues that impact the reliability, cost, performance, power dissipation, and reliability of the digital IC. This updated text reflects the ongoing (r)evolution in the world of digital integrated circuit design, caused by this move into the deep-submicron realm. This means increased importance of deep-submicron transistor effects, interconnect, signal integrity, high-performance and low-power design, timing, and clock distribution. In contrast to the first edition, the present text focuses entirely on CMOS ICs.http://bwrc.eecs.berkeley.edu/IcBookA Dynamic Companion
Even more than for the first edition, this book uses its companion website to evolve and grow over time. It contains complete Microsoft PowerPoint presentations covering all the material, updates. corrections, design projects, and extensive instructor material. Most importantly, all problem sets are now available on the website (and have been removed from the text).Outstanding Features of the Text
- It focuses solely on deep-submicron CMOS devices, the workhorses of today's digital integrated circuits. A simple transistor model for manual analysis, called the unified MOS model, has been developed and is used throughout.
- Design Examples stress the design of Digital ICs from a real-world perspective. Design challenges and guidelines are highlighted. 0.25-micron CMOS technology is used for all the examples and problems.
- Design Methodology inserts are interspersed throughout the text, highlighting the importance of methodology and tools in today's design process.
- A Perspective section at the end of each chapter gives an insight into future evolutions.
- Inbunden (hardback)
- Språk: Engelska
- Antal sidor: 761
- Utg.datum: 2002-12-01
- Upplaga: 2
- Förlag: Prentice Hall
- Medarbetare: Chandrakasan, Anantha / Nikolic, Borivoje
- Illustrationer: index
- Dimensioner: 235 x 180 x 4 mm
- Vikt: 1180 g
- Antal komponenter: 1
- Komponenter: International edition available ISBN 0131207644
- ISBN: 9780130909961
Fler böcker av Jan M Rabaey
Bloggat om Digital Integrated Circuits
(NOTE: Each chapter begins with an Introduction and concludes with a Summary, To Probe Further, and Exercises and Design Problems.)
I. THE FABRICS.1. Introduction.
A Historical Perspective. Issues in Digital Integrated Circuit Design. Quality Metrics of a Digital Design.2. The Manufacturing Process.
The CMOS Manufacturing Process. Design RulesThe Contract between Designer and Process Engineer. Packaging Integrated Circuits. PerspectiveTrends in Process Technology.3. The Devices.
The Diode. The MOS(FET) Transistor. A Word on Process Variations. Perspective: Technology Scaling.4. The Wire.
A First Glance. Interconnect ParametersCapitance, Resistance, and Inductance. Electrical Wire Models. SPICE Wire Models. Perspective: A Look into the Future.
II. A CIRCUIT PERSPECTIVE.5. The CMOS Inverter.
The Static CMOS InverterAn Intuitive Perspective. Evaluating the Robustness of the CMOS Inverter: The Static Behavior. Performance of CMOS Inverter: The Dynamic Behavior. Power, Energy, and Energy-Delay. Perspective: Technology Scaling and Its Impact on the Inverter Metrics.6. Designing Combinational Logic Gates in CMOS.
Static CMOS Design. Dynamic CMOS Design. How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era.7. Designing Sequential Logic Circuits.
Timing Metrics for Sequential Circuits. Classification of Memory Elements. Static Latches and Registers. Dynamic Latches and Registers. Pulse Registers. Sense-Amplifier Based Registers. Pipelining: An Approach to Optimize Sequential Circuits. Non-Bistable Sequential Circuits. Perspective: Choosing a Clocking Strategy.
III. A SYSTEM PERSPECTIVE.8. Implementation Strategies for Digital ICS.
From Custom to Semicustom and Structured-Array Design Approaches. Custom Circuit Design. Cell-Based Design Methodology. Array-Based Implementation Approaches. PerspectiveThe Implementation Platform of the Future.9. Coping with Interconnect.
Capacitive Parasitics. Resistive Parasitics. Inductive Parasitics. Advanced Interconnect Techniques. Perspective: Networks-on-a-Chip.10. Timing Issues in Digital Circuits.
Timing Classification of Digital Systems. Synchronous DesignAn In-Depth Perspective. Self-Timed Circuit Design. Synchronizers and Arbiters. Clock Synthesis and Synchronization Using a Phased-Locked Loop. Future Directions and Perspectives.11. Designing Arithmetic Building Blocks.
Datapaths in Digital Processor Architectures. The Adder. The Multiplier. The Shifter. Other Arithmetic Operators. Power and Spped Trade-Offs in Datapath Structures. Perspective: Design as a Trade-off.12. Designing Memory and Array Structures.
The Memory Core. Memory Peripher...