Digital Integrated Circuits

United States Edition

av Jan M Rabaey  (inbunden, 2002)

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Digital Integrated Circuits (inbunden)
  • Inbunden (hardback)
  • Språk: Engelska
  • Antal sidor: 761
  • Utg.datum: 2002-12-01
  • Upplaga: 2
  • Förlag: Prentice Hall
  • Medarbetare: Chandrakasan, Anantha / Nikolic, Borivoje
  • Illustrationer: index
  • Dimensioner: 235 x 180 x 4 mm
  • Vikt: 1180 g
  • Antal komponenter: 1
  • Komponenter: International edition available ISBN 0131207644
  • ISBN: 9780130909961

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Innehållsförteckning

(NOTE: Each chapter begins with an Introduction and concludes with a Summary, To Probe Further, and Exercises and Design Problems.)

I. THE FABRICS.

1. Introduction.

A Historical Perspective. Issues in Digital Integrated Circuit Design. Quality Metrics of a Digital Design.

2. The Manufacturing Process.

The CMOS Manufacturing Process. Design RulesThe Contract between Designer and Process Engineer. Packaging Integrated Circuits. PerspectiveTrends in Process Technology.

3. The Devices.

The Diode. The MOS(FET) Transistor. A Word on Process Variations. Perspective: Technology Scaling.

4. The Wire.

A First Glance. Interconnect ParametersCapitance, Resistance, and Inductance. Electrical Wire Models. SPICE Wire Models. Perspective: A Look into the Future.

II. A CIRCUIT PERSPECTIVE.

5. The CMOS Inverter.

The Static CMOS InverterAn Intuitive Perspective. Evaluating the Robustness of the CMOS Inverter: The Static Behavior. Performance of CMOS Inverter: The Dynamic Behavior. Power, Energy, and Energy-Delay. Perspective: Technology Scaling and Its Impact on the Inverter Metrics.

6. Designing Combinational Logic Gates in CMOS.

Static CMOS Design. Dynamic CMOS Design. How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era.

7. Designing Sequential Logic Circuits.

Timing Metrics for Sequential Circuits. Classification of Memory Elements. Static Latches and Registers. Dynamic Latches and Registers. Pulse Registers. Sense-Amplifier Based Registers. Pipelining: An Approach to Optimize Sequential Circuits. Non-Bistable Sequential Circuits. Perspective: Choosing a Clocking Strategy.

III. A SYSTEM PERSPECTIVE.

8. Implementation Strategies for Digital ICS.

From Custom to Semicustom and Structured-Array Design Approaches. Custom Circuit Design. Cell-Based Design Methodology. Array-Based Implementation Approaches. PerspectiveThe Implementation Platform of the Future.

9. Coping with Interconnect.

Capacitive Parasitics. Resistive Parasitics. Inductive Parasitics. Advanced Interconnect Techniques. Perspective: Networks-on-a-Chip.

10. Timing Issues in Digital Circuits.

Timing Classification of Digital Systems. Synchronous DesignAn In-Depth Perspective. Self-Timed Circuit Design. Synchronizers and Arbiters. Clock Synthesis and Synchronization Using a Phased-Locked Loop. Future Directions and Perspectives.

11. Designing Arithmetic Building Blocks.

Datapaths in Digital Processor Architectures. The Adder. The Multiplier. The Shifter. Other Arithmetic Operators. Power and Spped Trade-Offs in Datapath Structures. Perspective: Design as a Trade-off.

12. Designing Memory and Array Structures.

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