- Inbunden (Hardback)
- Antal sidor
- John Wiley & Sons Inc
- Jall, Garrett W.
- 25 x 245 x 163 mm
- Antal komponenter
- 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam
- 700 g
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High-Speed Digital System Design
A Handbook of Interconnect Theory and Design Practices
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Advanced Signal Integrity for High-Speed Digital Designs
Stephen H Hall, Howard L Heck
A synergistic approach to signal integrity for high-speed digital design This book is designed to provide contemporary readers with an understanding of the emerging high-speed signal integrity issues that are creating roadblocks in digital design....
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"...excellent guidebook for interconnect design...highly recommended for design engineers and recent graduates struggling to transition from theory to real-world design." (Choice, Vol. 38, No. 8, April 2001) "This is an excellent book for anyone who has basic circuit theory knowledge..." (E-Streams, Vol. 4, No. 8, August 2001)
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STEPHEN H. HALL is a Senior Design Engineer at Intel Corporation, Portland, Oregon. GARRETT W. HALL is a Silicon Systems Engineer at Intel Corporation. JAMES A. McCALL is a Senior Design Engineer at Intel Corporation.
Preface. 1. The Importance of Interconnect Design. 1.1 The Basics. 1.2 The Past and the Future. 2. Ideal Transmission Line Fundamentals. 2.1 Transmission Line Structures on a PCB or MCM. 2.2 Wave Propagation. 2.3 Transmission Line Parameters. 2.3.1 Characteristic Impedance. 2.3.2 Propagation Velocity, Time, and Distance. 2.3.3 Equivalent Circuit Models for SPICE Simulation. 2.4 Launching Initial Wave and Transmission Line Reflections. 2.4.1 Initial Wave. 2.4.2 Multiple Reflections. 2.4.3 Effect of Rise Time on Reflections. 2.4.4 Reflections From Reactive Loads. 2.4.5 Termination Schemes to Eliminate Reflections. 2.5 Additional Examples. 2.5.1 Problem. 2.5.2 Goals. 2.5.3 Calculating the Cross-Sectional Geometry of the PCB. 2.5.4 Calculating the Propagation Delay. 2.5.5 Determining the Wave Shape Seen at the Receiver. 2.5.6 Creating an Equivalent Circuit. 3. Crosstalk. 3.1 Mutual Inductance and Mutual Capacitance. 3.2 Inductance and Capacitance Matrix. 3.3 Field Simulators. 3.4 Crosstalk-Induced Noise. 3.5 Simulating Crosstalk Using Equivalent Circuit Models. 3.6 Crosstalk-Induced Flight Time and Signal Integrity Variations. 3.6.1 Effect of Switching Patterns on Transmission Line Performance. 3.6.2 Simulating Traces in a Multiconductor System Using a Single-Line Equivalent Model. 3.7 Crosstalk Trends. 3.8 Termination of Odd- and Even-Mode Transmission Line Pairs. 3.8.1 Pi Termination Network. 3.8.2 T Termination Network. 3.9 Minimization of Crosstalk. 3.10 Additional Examples. 3.10.1 Problem. 3.10.2 Goals. 3.10.3 Determining the Maximum Crosstalk-Induced Impedance and Velocity Swing. 3.10.4 Determining if Crosstalk Will Induce False Triggers. 4. Nonideal Interconnect Issues. 4.1 Transmission Line Losses. 4.1.1 Conductor DC Losses. 4.1.2 Dielectric DC Losses. 4.1.3 Skin Effect. 4.1.4 Frequency-Dependent Dielectric Losses. 4.2 Variations in the Dielectric Constant. 4.3 Serpentine Traces. 4.4 Intersymbol Interference. 4.5 Effects of 90 Bends. 4.6 Effect of Topology. 5. Connectors, Packages, and Vias. 5.1 Vias. 5.2 Connectors. 5.2.1 Series Inductance. 5.2.2 Shunt Capacitance. 5.2.3 Connector Crosstalk. 5.2.4 Effects of Inductively Coupled Connector Pin Fields. 5.2.5 EMI. 5.2.6 Connector Design Guidelines. 5.3 Chip Packages. 5.3.1 Common Types of Packages. 5.3.2 Creating a Package Model. 5.3.3 Effects of a Package. 5.3.4 Optimal Pin-Outs. 6. Nonideal Return Paths, Simultaneous Switching Noise, and Power Delivery. 6.1 Nonideal Current Return Paths. 6.1.1 Path of Least Inductance. 6.1.2 Signals Traversing a Ground Gap. 6.1.3 Signals That Change Reference Planes. 6.1.4 Signals Referenced to a Power or a Ground Plane. 6.1.5 Other Nonideal Return Path Scenarios. 6.1.6 Differential Signals. 6.2 Local Power Delivery Networks. 6.2.1 Determining the Local Decoupling Requirements for High-Speed I/O. 6.2.2 System-Level Power Delivery. 6.2.3 Choosing a Decoupling Capacitor. 6.2.4 Frequency Response of a Power Delivery System. 6.3 SSO/SSN. 6.3.1 Minimizing SSN. 7. Buffer Modeling. 7.1 Types of Models. 7.2 Basic CMOS Output Buffer. 7.2.1 Basic Operation. 7.2.2 Linear Modeling of the CMOS Buffer. 7.2.3 Behavioral Modeling of the Basic CMOS Buffer. 7.3 Output Buffers That Operate in the Saturation Region. 7.4 Conclusions. 8. Digital Timing Analysis. 8.1 Common-Clock Timing. 8.1.1 Common-Clock Timing Equations. 8.2 Source Synchronous Timing. 8.2.1 Source Synchronous Timing Equations. 8.2.2 Deriving Source Synchronous Timing Equations from an Eye Diagram. 8.2.3 Alternative Source Synchronous Schemes. 8.3 Alternative Bus Signaling Techniques. 8.3.1 Incident Clocking. 8.3.2 Embedded Clock. 9. Design Methodologies. 9.1 Timings. 9.1.1 Worst-Case Timing Spreadsheet. 9.1.2 Statistical Spreadsheets. 9.2 Timing Metrics, Signal Quality Metrics, and Test Loads. 9.2.1 Voltage Reference Uncertainty. 9.2.2 Simulation Reference Loads. 9.2.3 Flight Time. 9.2.4 Flight-Time Skew. 9.2.5 Signal Integrity. 9.3 Design Optimization. 9.3.1 Paper Analysis. 9.3.2 Routing St