Verilog 2001

`Mr. Sutherland was one of the principal engineers involved with the creation of the Verilog-2001 standard. The insights he provides in this book are a valuable resource for anyone seeking to understand these latest enhancements to the Verilog language.' Phil Moorby, Co-design Automation, Inc. `Stuart has done an outstanding job of explaining in detail all the new features of Verilog 2001. His book is very well written, easy to read and should serve as an invaluable supplement to the actual IEEE 1364-2001 standard.' Maq Mannan, DSM Technologies and Chair, IEEE 1364 Standards Group `This book is a must read for anyone who wants to use and take advantage of all the new powerful features in Verilog 2001. Mr Sutherland clearly describes all new constructs and compares them with the previous Verilog 1995 standard. His description of advantages of the new constructs and potential pitfalls is particularly useful when getting up to speed with Verilog 2001.' Anders Nordstrom, Nortel Networks, Ltd. `This book provides an excellent overview an explanation of the new Verilog 2001 features, the rationale for each new feature, and examples. Users of the new standard will find this book beneficial and easy to read.' Ben Cohen, Publisher, Trainer, Consultant `This book is a must-have for any Verilog programmer who wants to keep in touch with the latest developments in the language. [...]it could also serve as a good reference for beginners who can take advantage of the new features and adopt a muxch advanced coding style.' IEEE Circuits & Devices Magazine, September 2003

1. Combined port and data type declarations.- 2. ANSI C style module declarations.- 3. Module port parameter lists.- 4. ANSI C style UDP declarations.- 5. Variable initial value at declaration.- 6. ANSI C style task/function declarations.- 7. Automatic (re-entrant) tasks.- 8. Automatic (recursive) functions.- 9. Constant functions.- 10. Comma separated sensitivity lists.- 11. Combinational logic sensitivity lists.- 12. Implicit nets for continuous assignments.- 13. Disabling implicit net declarations.- 14. Variable vector part selects.- 15. Multidimensional arrays.- 16. Arrays of net and real data types.- 17. Array bit and part selects.- 18. Signed reg, net and port declarations.- 19. Signed based integer numbers.- 20. Signed functions.- 21. Sign conversion system functions.- 22. Arithmetic shift operators.- 23. Assignment width extension past 32 bits.- 24. Power operator.- 25. Attributes.- 26. Sized and typed parameter constants.- 27. Explicit in-line parameter redefinition.- 28. Fixed local parameters.- 29. Standard random number generator.- 30. Extended number of open files.- 31. Enhanced file I/O.- 32. String read and write system tasks.- 33. Enhanced invocation option testing.- 34. Enhanced conditional compilation.- 35. Source file and line compiler directive.- 36. Generate blocks.- 37. Configurations.- 38. On-detect pulse error propagation.- 39. Negative pulse detection.- 40. Enhanced input timing checks.- 41. Negative input timing constraints.- 42. Enhanced SDF file support.- 43. Extended VCD files.- 44. Enhanced PLA system tasks.- 45. Enhanced Verilog PLI support.- Appendix A: Verilog-2001 formal definition.- Appendix B: Verilog-2001 reserved words.