Digital VLSI Chip Design with Cadence and Synopsys CAD Tools

Professor Erik Brunvand is an associate professor in the School of Computing at the University of Utah. He has interests in computer architecture and VLSI systems in general, and self-timed and asynchronous systems in particular. One aspect of his research involves compiling concurrent communicating programs into asynchronous VLSI circuits. The current system allows programs written in a subset of occam, a concurrent message-passing programming language based on CSP, to be automatically compiled into a set of self-timed circuit modules suitable for manufacture as an integrated circuit. He is also interested in investigating the effects of asynchrony on computer systems architecture at a higher level. To explore these ideas he is building a series of prototype asynchronous computer systems out of FPGA and custom VLSI chips.

• 1 Introduction 11.1 CAD Tool Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.1.1 Custom VLSI and Cell Design Flow . . . . . . . . . . . . . . . . 31.1.2 Hierarchical Cell/Block ASIC Flow . . . . . . . . . . . . . . . . 31.2 What This Book Is and Isn’t . . . . . . . . . . . . . . . . . . . . . . . . 41.3 Bugs in the Tools? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.4 Tool Setup and Execution Scripts . . . . . . . . . . . . . . . . . . . . . . 61.5 Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . 7  2 Cadence DFII and ICFB 92.1 Cadence Design Framework . . . . . . . . . . . . . . . . . . . . . . . . 92.2 Starting Cadence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  3 Composer Schematic Capture 173.1 Starting Cadence and Making a NewWorking Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.2 Creating a New Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.2.1 Creating the Schematic View of a Full Adder . . . . . . . . . . . 193.2.2 Creating the Symbol View of a Full Adder . . . . . . . . . . . . . 263.2.3 Creating a Two-Bit Adder Using the FullAdder Bit . . . . . . . . 283.3 Schematics that Use Transistors . . . . . . . . . . . . . . . . . . . . . . 313.4 Printing Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.4.1 Modifying PostScript Plot Files . . . . . . . . . . . . . . . . . . 383.5 Variable, Pin, and Cell Naming Restrictions . . . . . . . . . . . . . . . . 393.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  4 Verilog Simulation 414.1 Verilog Simulation of Composer Schematics . . . . . . . . . . . . . . . . 444.1.1 Verilog-XL: Simulating a Schematic . . . . . . . . . . . . . . . . 454.1.2 NC Verilog: Simulating a Schematic . . . . . . . . . . . . . . . . 654.2 Behavioral Verilog Code in Composer . . . . . . . . . . . . . . . . . . . 694.2.1 Generating a Behavioral View . . . . . . . . . . . . . . . . . . . 724.2.2 Simulating a Behavioral View . . . . . . . . . . . . . . . . . . . 754.3 Stand-Alone Verilog Simulation . . . . . . . . . . . . . . . . . . . . . . 764.3.1 Verilog-XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784.3.2 NC Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804.3.3 VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874.4 Timing in Verilog Simulations . . . . . . . . . . . . . . . . . . . . . . . 904.4.1 Behavioral Versus Transistor Switch Simulation . . . . . . . . . . 944.4.2 Behavioral Gate Timing . . . . . . . . . . . . . . . . . . . . . . 964.4.3 Standard Delay Format (SDF) Timing . . . . . . . . . . . . . . . 994.4.4 Transistor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 1014.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107  5 Virtuoso Layout Editor 1095.1 An Inverter Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115.1.1 Starting Cadence icfb . . . . . . . . . . . . . . . . . . . . . . . . 1115.1.2 Making an Inverter Schematic . . . . . . . . . . . . . . . . . . . 1115.1.3 Making an Inverter Symbol . . . . . . . . . . . . . . . . . . . . 1125.2 Layout for an Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.2.1 Creating a New layout View . . . . . . . . . . . . . . . . . . . . 1135.2.2 Drawing an nmos Transistor . . . . . . . . . . . . . . . . . . . . 1135.2.3 Drawing a pmos Transistor . . . . . . . . . . . . . . . . . . . . . 1185.2.4 Assembling the Inverter from the Transistor Layouts . . . . . . . 1225.2.5 Using Hierarchy in Layout . . . . . . . . . . . . . . . . . . . . . 1285.2.6 Virtuoso Command Overview . . . . . . . . . . . . . . . . . . . 1305.3 Printing Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345.4 Design Rule Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345.4.1 DIVA Design Rule Checking . . . . . . . . . . . . . . . . . . . . 1345.5 Generating an Extracted View . . . . . . . . . . . . . . . . . . . . . . . 1405.6 Layout Versus Schematic Checking (LVS) . . . . . . . . . . . . . . . . . 1415.6.1 Generating an analog-extracted View . . . . . . . . . . . . . . . 1525.7 Overall Cell Design Flow (So Far...) . . . . . . . . . . . . . . . . . . . . 1535.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153  6 Standard Cell Design Template 1556.1 Standard Cell Geometry Specification . . . . . . . . . . . . . . . . . . . 1566.2 Standard Cell I/O Pin Placement . . . . . . . . . . . . . . . . . . . . . . 1586.3 Standard Cell Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . 1616.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162  7 Spectre Analog Simulator 1677.1 Simulating a Schematic (Transient Simulation) . . . . . . . . . . . . . . 1697.2 Simulation with the Spectre Analog Environment . . . . . . . . . . . . . 1717.3 Simulating with a Config View . . . . . . . . . . . . . . . . . . . . . . . 1767.4 Mixed Analog/Digital Simulation . . . . . . . . . . . . . . . . . . . . . 1827.4.1 Final Words about Mixed-Mode Simulation . . . . . . . . . . . . 1947.5 DC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987.5.1 Parametric Simulation . . . . . . . . . . . . . . . . . . . . . . . 2047.6 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2057.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213  8 Cell Characterization 2158.1 Liberty File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2158.1.1 Combinational Cell Definition . . . . . . . . . . . . . . . . . . . 2198.1.2 Sequential Cell Definition . . . . . . . . . . . . . . . . . . . . . 2218.1.3 Tristate Cell Definition . . . . . . . . . . . . . . . . . . . . . . . 2288.2 Cell Characterization with ELC . . . . . . . . . . . . . . . . . . . . . . 2308.2.1 Generating the ELC Netlist . . . . . . . . . . . . . . . . . . . . . 2308.2.2 Cell Naming and Encounter Library Characterizer . . . . . . . . 2438.2.3 Best, Typical, and Worst Case Characterization . . . . . . . . . . 2448.3 Cell Characterization with Spectre . . . . . . . . . . . . . . . . . . . . . 2448.4 Converting Liberty to Synopsys Database (db) Format . . . . . . . . . . 2508.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252  9 Verilog Synthesis 2539.1 Synopsys Design Compiler Synthesis with dc shell . . . . . . 2539.1.1 Basic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 2549.1.2 Scripted Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . 2589.1.3 Synopsys Design Vision GUI . . . . . . . . . . . . . . . . . . . . 2679.1.4 DesignWare Building Blocks . . . . . . . . . . . . . . . . . . . . 2769.2 Cadence RTL Compiler Synthesis . . . . . . . . . . . . . . . . . . . . . 2779.2.1 Scripted Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . 2779.2.2 Cadence RTL Compiler GUI . . . . . . . . . . . . . . . . . . . . 2809.3 Importing Structural Verilog into Cadence DFII . . . . . . . . . . . . . . 2859.4 Post-Synthesis Verilog Simulation . . . . . . . . . . . . . . . . . . . . . 2889.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295  10 Abstract Generation 29910.1 Reading Your Library into Abstract . . . . . . . . . . . . . . . . . . . . 30010.2 Finding Pins in Your Cells . . . . . . . . . . . . . . . . . . . . . . . . . 30310.3 The Extract Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30610.4 The Abstract Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30610.5 LEF File Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30610.6 Modifying the LEF File . . . . . . . . . . . . . . . . . . . . . . . . . . 30910.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311  11 SOC Encounter Place and Route 31311.1 Encounter GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31511.1.1 Reading In the Design . . . . . . . . . . . . . . . . . . . . . . . 31811.1.2 Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32311.1.3 Power Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . 32711.1.4 Placing the Standard Cells . . . . . . . . . . . . . . . . . . . . . 33311.1.5 First Optimization Phase . . . . . . . . . . . . . . . . . . . . . . 33311.1.6 Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . . . 33611.1.7 Post-CTS Optimization . . . . . . . . . . . . . . . . . . . . . . . 33811.1.8 Final Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33811.1.9 Post-Route Optimization . . . . . . . . . . . . . . . . . . . . . . 34311.1.10 Adding Filler Cells . . . . . . . . . . . . . . . . . . . . . . . . . 34511.1.11 Checking the Result . . . . . . . . . . . . . . . . . . . . . . . . 34511.1.12 Saving and Exporting the Placed and Routed Cell . . . . . . . . . 34911.1.13 Reading the Cell Back into Virtuoso . . . . . . . . . . . . . . . . 35211.2 Design Import with Configuration Files . . . . . . . . . . . . . . . . . . 35811.2.1 Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36111.3 SOC Encounter Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . 36111.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364  12 Chip Assembly 36712.1 Module Routing with ccar . . . . . . . . . . . . . . . . . . . . . . . . . 36712.1.1 Preparing a Placement with Virtuoso-XL . . . . . . . . . . . . . . 36912.1.2 Invoking the ccar Router . . . . . . . . . . . . . . . . . . . . . . 37412.2 Core to Pad Frame Routing with ccar . . . . . . . . . . . . . . . . . . . 38212.2.1 Copy the Pad Frame . . . . . . . . . . . . . . . . . . . . . . . . 38312.2.2 Modify the Frame schematic View . . . . . . . . . . . . . . . . 38512.2.3 Modify the Frame layout View . . . . . . . . . . . . . . . . . . 39012.2.4 Routing the Core to Frame with ccar . . . . . . . . . . . . . . . 39112.2.5 Metal Density Issues . . . . . . . . . . . . . . . . . . . . . . . . 39912.3 Final GDSII Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 39912.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405  13 Design Example 40913.1 Tiny MIPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41013.2 Tiny MIPS: Flat Tool Flow . . . . . . . . . . . . . . . . . . . . . . . . . 41613.2.1 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41613.2.2 Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . 42013.2.3 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43213.2.4 Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . 44313.3 Tiny MIPS: Hierarchical Tool Flow . . . . . . . . . . . . . . . . . . . . 44613.3.1 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44913.3.2 Place and Route into a Macro Block . . . . . . . . . . . . . . . . 44913.3.3 Preparing Custom Circuits for Hierarchy . . . . . . . . . . . . . 45113.3.4 Generating Abstract Views for Blocks . . . . . . . . . . . . . . . 45413.3.5 Place and Route with Macro Blocks . . . . . . . . . . . . . . . . 45613.3.6 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47013.3.7 Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . 47013.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470  A Tool and Setup Scripts 475A.1 Cadence Tool Installation . . . . . . . . . . . . . . . . . . . . . . . . . . 476A.2 Cadence Setup Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . 478A.2.1 setup-cadence: Basic Cadence Setup . . . . . . . . . . . . . . . 478A.2.2 setup-ncsu: Cadence Setup with NCSU Extensions . . . . . . . . 481A.3 Shell Scripts for Cadence Tools . . . . . . . . . . . . . . . . . . . . . . . 482A.3.1 syn-abstract: Start the Abstract Tool . . . . . . . . . . . . . . . 482A.3.2 cad-alf2lib: Convert the alf Notation from Encounter Library Characterizer to lib Notation . . . . . . . . . 482A.3.3 cad-elc: Start the Encounter Library Characterizer . . . . . . . . 483A.3.4 cad-ncsu: Start the DFII (icfb) Environment . . . . . . . . . . . 484A.3.5 cad-soc: Start the SOC Encounter Place and Route Tool . . . . . 484A.3.6 sim-ncg: Startup Script for the NC Verilog Simulator, with GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485A.3.7 sim-xlg: Startup Script for the Verilog-XL simulator, with GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485A.3.8 sptr2elc: Perl Script for Converting Spectre Netlists to Encounter Library Characterizer Netlists . .  . 486A.3.9 syn-rtlg: Start the RTL Compiler Synthesis Tool, with GUI . . . 487A.4 Synopsys Tool Installation . . . . . . . . . . . . . . . . . . . . . . . . . 488A.5 Synopsys Setup Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . 489A.5.1 setup-synopsys: Basic Synopsys Setup . . . . . . . . . . . . . . 489A.6 Shell Scripts for Synopsys Tools . . . . . . . . . . . . . . . . . . . . . . 492A.6.1 sim-vcs: Startup Script for the VCS Verilog Simulator . . . . . . 492A.6.2 sim-simv: Startup Script for the simv Simulator Resulting from VCS Execution  . . . . . . . . . . . . . . 493A.6.3 syn-dc: Startup Script for Design Compiler Synthesis . . . . . . 494A.6.4 syn-dv: Startup Script for Design Compiler using the Design Vision GUI . .. . . . . . . . . 494A.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495  B Scripts to Drive the Tools 497B.1 Tcl Script Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497B.2 Cadence Tool Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499B.2.1 Encounter Library Characterizer Cell Characterization . . . . . . 500B.2.2 Cell Characterization with Spectre . . . . . . . . . . . . . . . . . 504B.2.3 SOC Encounter Place and Route . . . . . . . . . . . . . . . . . . 509B.2.4 RTL Compiler Synthesis . . . . . . . . . . . . . . . . . . . . . . 516B.2.5 ccar Chip Assembly Tool . . . . . . . . . . . . . . . . . . . . . 517B.3 Synopsys Tool Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519B.3.1 Synopsys Design Compiler Script Files . . . . . . . . . . . . . . 519B.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524  C Technology and Cell Libraries 525C.1 NCSU Cadence Design Kit CDK1.5 Installation . . . . . . . . . . . . . . 525C.1.1 .cdsinit: Local Modifications . . . . . . . . . . . . . . . . . . . 526C.1.2 .cdsenv: Local Modifications . . . . . . . . . . . . . . . . . . . 529C.1.3 UofU TechLib ami06: Local Modifications . . . . . . . . . . . 530C.2 Example Standard Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . 535C.2.1 Example Liberty File . . . . . . . . . . . . . . . . . . . . . . . 536C.2.2 LEF File Technology Header . . . . . . . . . . . . . . . . . . . . 551C.2.3 LEF File MACRO Examples . . . . . . . . . . . . . . . . . . . . 554C.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563Bibliography 565Index 567