Daniel Groe – författare

This book brings together a selection of the best papers from the twentiethedition of the Forum on specification and Design Languages Conference (FDL), which took place on September 18-20, 2017, in Verona, Italy.  FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems.

This book brings together a selection of the best papers from the twenty-first edition of the Forum on specification and Design Languages Conference (FDL), which took place on September 10-12, 2018, in Munich, Germany.  FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems.

This book presents a comprehensive set of techniques that enhance all key aspects of a modern Virtual Prototype (VP)-based design flow. The authors emphasize automated formal verification methods, as well as advanced coverage-guided analysis and testing techniques, tailored for SystemC-based VPs and also the associated Software (SW). Coverage also includes VP modeling techniques that handle functional as well as non-functional aspects and also describes correspondence analyses between the Hardware- and VP-level to utilize information available at different levels of abstraction. All approaches are discussed in detail and are evaluated extensively, using several experiments to demonstrate their effectiveness in enhancing the VP-based design flow. Furthermore, the book puts a particular focus on the modern RISC-V ISA, with several case-studies covering modeling as well as VP and SW verification aspects.

This book describes recent findings in the domain of Boolean logic and Boolean algebra, covering application domains in circuit and system design, but also basic research in mathematics and theoretical computer science. Content includes invited chapters and a selection of the best papers presented at the 14th annual International Workshop on Boolean Problems.

This book describes a comprehensive combination of methodologies that strongly enhance the modern Virtual Prototype (VP)-based verification flow for heterogeneous systems-on-chip (SOCs). In particular, the book combines verification and analysis aspects across various stages of the VP-based verification flow, providing a new perspective on verification by leveraging advanced techniques, like metamorphic testing, data flow testing, and information flow testing. In addition, the book puts a strong emphasis on advanced coverage-driven methodologies to verify the functional behavior of the SOC as well as ensure its security.

Dieses Buch stellt eine umfassende Reihe von Techniken vor, die alle wichtigen Aspekte eines modernen Virtual Prototype (VP)-basierten Entwurfsablaufs verbessern. Die Autoren legen den Schwerpunkt auf automatisierte formale Verifikationsmethoden sowie auf fortgeschrittene, abdeckungsgeleitete Analyse- und Testtechniken, die auf SystemC-basierte VP und die zugehörige Software (SW) zugeschnitten sind. Die Abdeckung umfasst auch VP-Modellierungstechniken, die sowohl funktionale als auch nicht-funktionale Aspekte behandeln, und beschreibt zudem Korrespondenzanalysen zwischen der Hardware- und VP-Ebene, um die auf verschiedenen Abstraktionsebenen verfügbaren Informationen zu nutzen. Alle Ansätze werden ausführlich diskutiert und anhand mehrerer Experimente evaluiert, um ihre Effektivität bei der Verbesserung des VP-basierten Entwurfsablaufs zu demonstrieren. Darüber hinaus legt das Buch einen besonderen Schwerpunkt auf den modernen RISC-V ISA, mit mehreren Fallstudien, die sowohl Aspekteder Modellierung als auch der VP- und SW-Verifikation abdecken.

This book addresses the challenging tasks of verifying and debugging structurally complex multipliers. In the area of verification, the authors first investigate the challenges of Symbolic Computer Algebra (SCA)-based verification, when it comes to proving the correctness of multipliers. They then describe three techniques to improve and extend SCA: vanishing monomials removal, reverse engineering, and dynamic backward rewriting. This enables readers to verify a wide variety of multipliers, including highly complex and optimized industrial benchmarks. The authors also describe a complete debugging flow, including bug localization and fixing, to find the location of bugs in structurally complex multipliers and make corrections.

Dieses Buch beschreibt eine umfassende Kombination von Methoden, die den modernen Virtual Prototype (VP)-basierten Verifikationsfluss für heterogene Systems-on-Chip (SOCs) stark verbessern. Insbesondere kombiniert das Buch Verifikations- und Analyseaspekte über verschiedene Stufen des VP-basierten Verifikationsflusses hinweg und bietet eine neue Perspektive auf die Verifikation, indem es fortschrittliche Techniken wie metamorphes Testen, Datenfluss-Testen und Informationsfluss-Testen einsetzt. Darüber hinaus legt das Buch einen starken Schwerpunkt auf fortschrittliche, abdeckungsorientierte Methoden zur Verifizierung des funktionalen Verhaltens des SOC sowie zur Gewährleistung seiner Sicherheit.

This book describes several versatile hardware analysis techniques that tackle existing and new challenges. These techniques cover different phases of the hardware development process, including the verification, debugging, and post-synthesis optimization phases.  The authors introduce the Waveform Analysis Language (WAL), which allows users to code analysis tasks in the form of programs that run on waveforms. The book covers processor verification, formal microcode verification, programmable automated waveform analysis demonstrated for a large variety of previously manual analysis tasks, as well as netlist optimization leveraging formal methods. All methods are available as open source, typically include examples on RISC-V analysis problems, providing a strong foundation for the community.

This book describes reliable and efficient design automation techniques for the design and implementation of an approximate computing system. The authors address the important facets of approximate computing hardware design - from formal verification and error guarantees to synthesis and test of approximation systems. They provide algorithms and methodologies based on classical formal verification, synthesis and test techniques for an approximate computing IC design flow.  This is one of the first books in Approximate Computing that addresses the design automation aspects, aiming for not only sketching the possibility, but providing a comprehensive overview of different tasks and especially how they can be implemented.