Wolfgang J. Paul – författare

This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.

It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:

• MIPS instruction set architecture (ISA) for application and for system programming

• cache coherent memory system

• store buffers in front of the data caches

• interrupts and exceptions

• pipelined processors: the classical five-stage pipeline is extended by two pipeline

stages for address translation

• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)

• I/O-interrupt controller and a disk

This monograph is based on the third author''s lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.

The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.

Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.

The pillars of the bridge on the cover of this book date from the Roman Empire and they are in daily use today, an example of conventional engineering at its best. Modern commodity operating systems are examples of current system programming at its best, with bugs discovered and fixed on a weekly or monthly basis. This book addresses the question of whether it is possible to construct computer systems that are as stable as Roman designs.

The authors successively introduce and explain specifications, constructions and correctness proofs of a simple MIPS processor; a simple compiler for a C dialect; an extension of the compiler handling C with inline assembly, interrupts and devices; and the virtualization layer of a small operating system kernel. A theme of the book is presenting system architecture design as a formal discipline, and in keeping with this the authors rely on mathematics for conciseness and precision of arguments to an extent common in other engineering fields.

This textbook is based on the authors'' teaching and practical experience, and it is appropriate for undergraduate students of electronics engineering and computer science. All chapters are supported with exercises and examples.