Amos R. Omondi – författare

During the 1980s and early 1990s there was signi?cant work in the design and implementation of hardware neurocomputers. Nevertheless, most of these efforts may be judged to have been unsuccessful: at no time have have ha- ware neurocomputers been in wide use. This lack of success may be largely attributed to the fact that earlier work was almost entirely aimed at developing custom neurocomputers, based on ASIC technology, but for such niche - eas this technology was never suf?ciently developed or competitive enough to justify large-scale adoption. On the other hand, gate-arrays of the period m- tioned were never large enough nor fast enough for serious arti?cial-neur- network (ANN) applications. But technology has now improved: the capacity and performance of current FPGAs are such that they present a much more realistic alternative. Consequently neurocomputers based on FPGAs are now a much more practical proposition than they have been in the past. This book summarizes some work towards this goal and consists of 12 papers that were selected, after review, from a number of submissions. The book is nominally divided into three parts: Chapters 1 through 4 deal with foundational issues; Chapters 5 through 11 deal with a variety of implementations; and Chapter 12 looks at the lessons learned from a large-scale project and also reconsiders design issues in light of current and future technology.

During the 1980s and early 1990s there was signi?cant work in the design and implementation of hardware neurocomputers. Nevertheless, most of these efforts may be judged to have been unsuccessful: at no time have have ha- ware neurocomputers been in wide use. This lack of success may be largely attributed to the fact that earlier work was almost entirely aimed at developing custom neurocomputers, based on ASIC technology, but for such niche - eas this technology was never suf?ciently developed or competitive enough to justify large-scale adoption. On the other hand, gate-arrays of the period m- tioned were never large enough nor fast enough for serious arti?cial-neur- network (ANN) applications. But technology has now improved: the capacity and performance of current FPGAs are such that they present a much more realistic alternative. Consequently neurocomputers based on FPGAs are now a much more practical proposition than they have been in the past. This book summarizes some work towards this goal and consists of 12 papers that were selected, after review, from a number of submissions. The book is nominally divided into three parts: Chapters 1 through 4 deal with foundational issues; Chapters 5 through 11 deal with a variety of implementations; and Chapter 12 looks at the lessons learned from a large-scale project and also reconsiders design issues in light of current and future technology.

The Microarchitecture of Pipelined and Superscalar Computers provides an authoritative treatment of the implementation (i.e. microarchitecture) of computer architectures. The subject matter covered is the collection of techniques that are used to achieve the highest performance in single-processor machines; these techniques center the exploitation of low-level parallelism (temporal and spatial) in the processing of machine instructions. The book gives a coherent picture of caches, pipelines and their control, and branch prediction. It is the first such publication to treat these topics together. The Microarchitecture of Pipelined and Superscalar Computers covers the fundamentals of the subject by outlining the general principles and ideas. These are then demonstrated by selected case studies taken from practical machines. The Microarchitecture of Pipelined and Superscalar Computers has been specifically developed as a textbook for advanced undergraduate or graduate level instruction. It also makes an invaluable reference for microprocessor design engineers and those seeking to pursue research in the area.

The development of neural networks has now reached the stage where they are employed in a large variety of practical contexts. However, to date the majority of such implementations have been in software. While it is generally recognised that hardware implementations could, through performance advantages, greatly increase the use of neural networks, to date the relatively high cost of developing Application-Specific Integrated Circuits (ASICs) has meant that only a small number of hardware neurocomputers has gone beyond the research-prototype stage. The situation has now changed dramatically: with the appearance of large, dense, highly parallel FPGA circuits it has now become possible to envisage putting large-scale neural networks in hardware, to get high performance at low costs. This in turn makes it practical to develop hardware neural-computing devices for a wide range of applications, ranging from embedded devices in high-volume/low-cost consumer electronics to large-scale stand-alone neurocomputers. Not surprisingly, therefore, research in the area has recently rapidly increased, and even sharper growth can be expected in the next decade or so.Nevertheless, the many opportunities offered by FPGAs also come with many challenges, since most of the existing body of knowledge is based on ASICs (which are not as constrained as FPGAs). These challenges range from the choice of data representation, to the implementation of specialized functions, through to the realization of massively parallel neural networks; and accompanying these are important secondary issues, such as development tools and technology transfer. All these issues are currently being investigated by a large number of researchers, who start from different bases and proceed by different methods, in such a way that there is no systematic core knowledge to start from, evaluate alternatives, validate claims, and so forth. FPGA Implementations of Neural Networks aims to be a timely one that fill this gap in three ways: First, it will contain appropriate foundational material and therefore be appropriate for advanced students or researchers new to the field. Second, it will capture the state of the art, in both depth and breadth and therefore be useful researchers currently active in the field. Third, it will cover directions for future research, i.e. embryonic areas as well as more speculative ones.

The Microarchitecture of Pipelined and Superscalar Computers provides an authoritative treatment of the implementation (i.e. microarchitecture) of computer architectures. The subject matter covered is the collection of techniques that are used to achieve the highest performance in single-processor machines; these techniques center the exploitation of low-level parallelism (temporal and spatial) in the processing of machine instructions. The book gives a coherent picture of caches, pipelines and their control, and branch prediction. It is the first such publication to treat these topics together. The Microarchitecture of Pipelined and Superscalar Computers covers the fundamentals of the subject by outlining the general principles and ideas. These are then demonstrated by selected case studies taken from practical machines. The Microarchitecture of Pipelined and Superscalar Computers has been specifically developed as a textbook for advanced undergraduate or graduate level instruction. It also makes an invaluable reference for microprocessor design engineers and those seeking to pursue research in the area.

This book is intended to serve as a textbook for a second course in the im­ plementation (Le. microarchitecture) of computer architectures. The subject matter covered is the collection of techniques that are used to achieve the highest performance in single-processor machines; these techniques center the exploitation of low-level parallelism (temporal and spatial) in the processing of machine instructions. The target audience consists students in the final year of an undergraduate program or in the first year of a postgraduate program in computer science, computer engineering, or electrical engineering; professional computer designers will also also find the book useful as an introduction to the topics covered. Typically, the author has used the material presented here as the basis of a full-semester undergraduate course or a half-semester post­ graduate course, with the other half of the latter devoted to multiple-processor machines. The background assumed of the reader is a good first course in computer architecture and implementation - to the level in, say, Computer Organization and Design, by D. Patterson and H. Hennessy - and familiarity with digital-logic design. The book consists of eight chapters: The first chapter is an introduction to all of the main ideas that the following chapters cover in detail: the topics covered are the main forms of pipelining used in high-performance uniprocessors, a taxonomy of the space of pipelined processors, and performance issues. It is also intended that this chapter should be readable as a brief "stand-alone" survey.

Computer-Hardware Evaluation of Mathematical Functions provides a thorough up-to-date understanding of the methods used in computer hardware for the evaluation of mathematical functions: reciprocals, square-roots, exponentials, logarithms, trigonometric functions, hyperbolic functions, etc. It discusses how the methods are derived, how they work, and how well they work. The methods are divided into four core themes: CORDIC, normalization, table look-up, and polynomial approximations. In each case, the author carefully considers the mathematical derivation and basis of the relevant methods, how effective they are (including mathematical errors analysis), and how they can be implemented in hardware.This book is an excellent resource for any student or researcher seeking a comprehensive, yet easily understandable, explanation of how computer chips evaluate mathematical functions.

Residue number systems (RNSs) and arithmetic are useful for several reasons. First, a great deal of computing now takes place in embedded processors, such as those found in mobile devices, for which high speed and low-power consumption are critical; the absence of carry propagation facilitates the realization of high-speed, low-power arithmetic. Second, computer chips are now getting to be so dense that full testing will no longer be possible; so fault tolerance and the general area of computational integrity have become more important. RNSs are extremely good for applications such as digital signal processing, communications engineering, computer security (cryptography), image processing, speech processing, and transforms, all of which are extremely important in computing today.This book provides an up-to-date account of RNSs and arithmetic. It covers the underlying mathematical concepts of RNSs; the conversion between conventional number systems and RNSs; the implementation of arithmetic operations; various related applications are also introduced. In addition, numerous detailed examples and analysis of different implementations are provided.

This book is an introduction to the implementation of cryptosystems at that level. The aforementioned arithmetic is mostly the arithmetic of finite fields, and the book is essentially one on the arithmetic of prime fields and binary fields in the context of cryptography.

Modern cryptosystems, used in numerous applications that require secrecy or privacy - electronic mail, financial transactions, medical-record keeping, government affairs, social media etc. - are based on sophisticated mathematics and algorithms that in implementation involve much computer arithmetic. And for speed it is necessary that the arithmetic be realized at the hardware (chip) level. This book is an introduction to the implementation of cryptosystems at that level.The aforementioned arithmetic is mostly the arithmetic of finite fields, and the book is essentially one on the arithmetic of prime fields and binary fields in the context of cryptography. The book has three main parts. The first part is on generic algorithms and hardware architectures for the basic arithmetic operations: addition, subtraction, multiplication, and division. The second part is on the arithmetic of prime fields. And the third part is on the arithmetic of binary fields. The mathematical fundamentals necessary for the latter two parts are included, as are descriptions of various types of cryptosystems, to provide appropriate context.This book is intended for advanced-level students in Computer Science, Computer Engineering, and Electrical and Electronic Engineering. Practitioners too will find it useful, as will those with a general interest in "hard" applications of mathematics.