José T. de Sousa – författare
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3 produkter
3 produkter
1 596 kr
Skickas inom 10-15 vardagar
This title explains how to synthesize digital diagnostic sequences for wire interconnects using boundary-scan, and how to assess the quality of those sequences. Its importance has to do with designing complex electronic systems using pre-designed intellectual property (IP) cores, which is becoming increasingly popular. Since tests for pre-designed cores can be supplied with the cores themselves, the only additional tests that need to be developed to test and diagnose the entire system are those for wire interconnects between the cores. Besides the trivial solutions that are often used to solve this problem, there are many more methods that enable significant optimizations of test vector length and/or diagnostic resolution. The book surveys all existing methods of this kind and proposes new ones. In the new approach circuit and interconnect faults are carefully modeled, and graph techniques are applied to solve the problem. The original feature of the new method is the fact that it can be adjusted to provide shorter test sequences and/or greater diagnostic resolution.The effectiveness of existing and proposed methods is then evaluated using real electronic assemblies and published statistical data for an actual manufacturing process from HP.
1 596 kr
Skickas inom 10-15 vardagar
Boundary-Scan Interconnect Diagnosis explains how to synthesize digital diagnostic sequences for wire interconnects using boundary-scan, and how to assess the quality of those sequences. Its importance has to do with designing complex electronic systems using pre-designed intellectual property (IP) cores, which is becoming increasingly popular nowadays. Since tests for pre-designed cores can be supplied with the cores themselves, the only additional tests that need to be developed to test and diagnose the entire system are those for wire interconnects between the cores. Besides the trivial solutions that are often used to solve this problem, there are many more methods that enable significant optimizations of test vector length and/or diagnostic resolution. The book surveys all existing methods of this kind and proposes new ones. In the new approach circuit and interconnect faults are carefully modeled, and graph techniques are applied to solve the problem. The original feature of the new method is the fact that it can be adjusted to provide shorter test sequences and/or greater diagnostic resolution. The effectiveness of existing and proposed methods is then evaluated using real electronic assemblies and published statistical data for an actual manufacturing process from HP.
653 kr
Skickas inom 10-15 vardagar
This book constitutes the refereed proceedings of the 13th International Conference on Field-Programmable Logic and Applications, FPL 2003, held in Lisbon, Portugal in September 2003.The 90 revised full papers and 56 revised poster papers presented were carefully reviewed and selected from 216 submissions. The papers are organized in topical sections on technologies and trends, communications applications, high level design tools, reconfigurable architecture, cryptographic applications, multi-context FPGAs, low-power issues, run-time reconfiguration, compilation tools, asynchronous techniques, bio-related applications, codesign, reconfigurable fabrics, image processing applications, SAT techniques, application-specific architectures, DSP applications, dynamic reconfiguration, SoC architectures, emulation, cache design, arithmetic, bio-inspired design, SoC design, cellular applications, fault analysis, and network applications.