Stuart K. Tewksbury – författare

From the perspective of complex systems, conventional Ie's can be regarded as "discrete" devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys­ tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term "wafer­ level" is perhaps more appropriate than "wafer-scale". A "wafer-level" monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, "wafer-scale" merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.

Computing systems researchers confront two serious problems. (1) The increasingly monolithic, or pseudo-monolithic, integration of complex com­ puting functions and systems imposes an environment which integrates ad­ vanced principles and techniques from a broad variety of fields. Researchers not only must confront the increased complexity of topics in their specialty field but also must develop a deeper general understanding of a broadening number of fields. (2) There has been a proliferation of journals, books, workshops and conferences through which research results are reported. Remaining familiar with recent advances in our specific fields is a major challenge. Casually browsing through journals and conference proceedings to remain aware of developments in areas outside our specialization has become an even greater challenge. Frontiers of Computing Systems Research has been established to ad­ dress these two issues. With the assistance of an advisory board of experts from a wide variety of specialized areas, we hope to provide roughly annual volumes of invited chapters on a broad range of topics and designed for an interdisciplinary research audience. No single volume can cover all the rel­ evant topics and no single article can convey the full set of directions being pursued within a given topic. For this reason, a chapter listing technical reports available from universities is also included. Often, such unpub­ lished reports are designed for a general research audience and provide a good, informal look at trends in specialized research topics.

From the perspective of complex systems, conventional Ie's can be regarded as "discrete" devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys­ tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term "wafer­ level" is perhaps more appropriate than "wafer-scale". A "wafer-level" monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, "wafer-scale" merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.

Computing systems researchers confront two serious problems. (1) The increasingly monolithic, or pseudo-monolithic, integration of complex com­ puting functions and systems imposes an environment which integrates ad­ vanced principles and techniques from a broad variety of fields. Researchers not only must confront the increased complexity of topics in their specialty field but also must develop a deeper general understanding of a broadening number of fields. (2) There has been a proliferation of journals, books, workshops and conferences through which research results are reported. Remaining familiar with recent advances in our specific fields is a major challenge. Casually browsing through journals and conference proceedings to remain aware of developments in areas outside our specialization has become an even greater challenge. Frontiers of Computing Systems Research has been established to ad­ dress these two issues. With the assistance of an advisory board of experts from a wide variety of specialized areas, we hope to provide roughly annual volumes of invited chapters on a broad range of topics and designed for an interdisciplinary research audience. No single volume can cover all the rel­ evant topics and no single article can convey the full set of directions being pursued within a given topic. For this reason, a chapter listing technical reports available from universities is also included. Often, such unpub­ lished reports are designed for a general research audience and provide a good, informal look at trends in specialized research topics.

From the perspective of complex systems, conventional Ie''s can be regarded as "discrete" devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie''s) to one of integrated sys­ tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit''s area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term "wafer­ level" is perhaps more appropriate than "wafer-scale". A "wafer-level" monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, "wafer-scale" merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.

Intended for an interdisciplinary audience involved in computer systems research, this second volume presents technical information on emerging topics in the field.

Intended for an interdisciplinary audience involved in computer systems research, this second volume presents technical information on emerging topics in the field.

The 1987 Princeton Workshop on Algorithm, Architecture and Technology Issues for Models of Concurrent Computation was organized as an interdisciplinary work­ shop emphasizing current research directions toward concurrent computing systems. With participants from several different fields of specialization, the workshop cov­ ered a wide variety of topics, though by no means a complete cross section of issues in this rapidly moving field. The papers included in this book were prepared for the workshop and, taken together, provide a view of the broad range of issues and alternative directions being explored. To organize the various papers, the book has been divided into five parts. Part I considers new technology directions. Part II emphasizes underlying theoretical issues. Communication issues, which are ad­ dressed in the majority of papers, are specifically highlighted in Part III. Part IV includes papers stressing the fault tolerance and reliability of systems. Finally, Part V includes systems-oriented papers, where the system ranges from VLSI circuits through powerful parallel computers. Much of the initial planning of the workshop was completed through an informal AT&T Bell Laboratories group consisting of Mehdi Hatamian, Vijay Kumar, Adri­ aan Ligtenberg, Sailesh Rao, P. Subrahmanyam and myself. We are grateful to Stuart Schwartz, both for the support of Princeton University and for his orga­ nizing local arrangements for the workshop, and to the members of the organizing committee, whose recommendations for participants and discussion topics were par­ ticularly helpful. A. Rosenberg, and A. T.