T.N. Vijaykumar – författare

WelcometotheproceedingsofthePower-AwareComputerSystems(PACS2002) workshopheld in conjunction with the 8th InternationalSymposium on High PerformanceComputerArchitecture(HPCA-8). Improvementsincomputers- temperformancehavebeenaccompaniedbyanalarmingincreaseinpowerand energydissipation,leading tohigher costandlowerreliabilityinallcomputer systemsmarketsegments. Thehigherpower/energydissipationhasalsosign- icantlyreducedbatterylife inportablesystems. Whilecircuit-leveltechniques continuetoreducepowerandenergy,alllevelsofcomputersystemsarebeing usedtoaddresspowerandenergyissues. PACS2002wasthesecondworkshopin itsseriestoaddresspower-/energy-awarenessatalllevelsofcomputersystems andbroughttogetherexpertsfromacademiaandindustry. Theseproceedingsincluderesearchpapersspanningawidespectrumof- eas in power-aware systems. We have grouped the papers into the following categories:(1)power-awarearchitectureandmicroarchitecture,(2)power-aware real-time systems, (3) power modeling and monitoring, and (4) power-aware operatingsystemsandcompilers. The?rstgroupofpapersproposepower-awaretechniquesfortheprocessor pipeline using adaptiveresizing of power-hungrymicroarchitecturalstructures andclockgating,andpower-awarecachedesignbyavoidingtagchecksin- riodswhenthetagshavenotchanged.Thisgroupalsoincludesideastoadapt energyandperformancedynamicallybydetectingregionsofapplicationatr- timewherethesupplyvoltagemaybescaledtoreducepowerwithabounded decrease in performance. Lastly, a paper on multiprocessor designs trades o? computingcapacityandfunctionalityforimprovedenergypercyclebysched- ing simple tasks on low-end and low-energy processorsand complex tasks on high-endprocessors. Thesecondgroupofpaperstargetreal-timesystemsincludingideasonal- complexityheuristicwhichschedulesreal-timetaskssuchthatnotaskmissesits deadlineandthetotalenergysavingsaremaximized. Theotherpapersinthis group(1)tunethesystem-levelparallelismtothecurrent-levelofpower/energy availabilityandoptimizethesystempowerutilization,and(2)performadaptive texturemappinginreal-time3Dgraphicssystemsbasedonamodelofhuman visualperceptiontoachievesigni?cantpowersavingswithoutnoticeableimage qualitydegradation. Thethirdgroupofpapersfocusonpowermodelingandmonitoringincluding statisticalpro?lingtodetectsoftwarehotspotsofpower,andusingPetriNetsto modelDRAMpowerpolicies. Thisgroupalsoincludesasimulatorforevaluating theperformanceandpowerofdynamicvoltagescalingalgorithms.Thelast groupconcentratesonOS and compilersfor lowpower. The ?rst paperproposesapplication-issueddirectivestosetthepowermodesindevices suchasadiskdrive. Thesecondpaperproposespoliciesforcluster-widepower VI Preface management. Thepoliciesemploycombinationsofdynamicvoltagescalingand turningonando?toreduceoverallclusterpower. PACS2002wasahighlysuccessfulforumduetothehigh-qualitysubmissions, theenormouse?ortsoftheprogramcommitteeandthekeynotespeaker,andthe attendees. WewouldliketothankRonnyRonenforanexcellentkeynotespeech, showingthetechnologicalscalingtrendsandtheirimpactonenergy/powerc- sumption in general-purposemicroprocessors,and pinpointing recentmicro- chitecturalstrategiestoachievemorepower-e?cientmicroprocessors. Wewould like to also thank Antonio Gonzalez, Andreas Moshovos,John Kalamatianos, andothermembersoftheHPCA-8organizingcommitteewhohelpedarrange forlocalaccomodationandpublicizetheworkshop. February2002 BabakFalsa?andT. N. Vijaykumar PACS2002 Program Committee BabakFalsa?,CarnegieMellonUniversity(co-chair) T. N.Vijaykumar,PurdueUniversity(co-chair) DaveAlbonesi,UniversityofRochester KrsteAsanovic,MassachusettsInstituteofTechnology IrisBahar,BrownUniversity LucaBenini,UniversityofBologna DougCarmean,Intel Yuen Chan,IBM KeithFarkas,CompaqWRL MaryJaneIrwin,PennsylvaniaStateUniversity StefanosKaxiras,AgereSystems PeterKogge,UniversityofNotreDame UliKremer,RutgersUniversity AlvinLebeck,DukeUniversity AndreasMoshovos,UniversityofToronto RajRajkumar,CarnegieMellonUniversity KaushikRoy,PurdueUniversity Table of Contents Power-Aware Architecture/Microarchitecture Early-StageDe?nitionofLPX:ALowPowerIssue-ExecuteProcessor ...1 P. Bose,D. Brooks,A. Buyuktosunoglu,P. Cook,K. Das,P. Emma, M. Gschwind,H. Jacobson,T. Karkhanis,P. Kudva,S. Schuster, J. Smith,V. Srinivasan,V. Zyuban,D. Albonesi,andS. Dwarkadas DynamicTag-CheckOmission: ALowPowerInstructionCacheArchitecture ExploitingExecutionFootprints ...18 KojiInoue,VasilyMoshnyaga,andKazuakiMurakami AHardwareArchitecture forDynamicPerformanceandEnergyAdaptation...33 PhillipStanley-Marbell,MichaelS. Hsiao,andUlrichKremer Multi-processorComputerSystemHavingLowPowerConsumption ...53 C. MichaelOlsenandL.AlexMorrow Power-Aware Real-TimeSystems AnIntegratedHeuristicApproach toPower-AwareReal-TimeScheduling...68 PedroMejia,EugeneLevner,andDanielMoss'e Power-AwareTaskMotionforEnhancingDynamicRange ofEmbeddedSystemswithRenewableEnergySources ...84 JinfengLiu,PaiH. Chou,andNaderBagherzadeh ALow-PowerContent-AdaptiveTextureMappingArchitecture forReal-Time3DGraphics ...99 JeongseonEuh,JeevanChittamuru,andWayneBurleson Power Modelingand Monitoring Energy-DrivenStatisticalSampling:DetectingSoftwareHotspots ...110 FayChang,KeithI. Farkas,andParthasarathyRanganathan ModelingofDRAMPowerControlPolicies UsingDeterministicandStochasticPetriNets ...130 XiaoboFan,CarlaS. Ellis,andAlvinR. Lebeck SimDVS:AnIntegratedSimulationEnvironment forPerformanceEvaluationofDynamicVoltageScalingAlgorithms ...

Welcome to the proceedings of the Power-Aware Computer Systems (PACS 2004) workshop held in conjunction with the 37th Annual International Sym- sium on Microarchitecture (MICRO-37). The continued increase of power and energy dissipation in computer systems has resulted in higher cost, lower re- ability, and reduced battery life in portable systems. Consequently, power and energy have become ?rst-class constraints at all layers of modern computer s- tems. PACS 2004 is the fourth workshop in its series to explore techniques to reduce power and energy at all levels of computer systems and brings together academic and industry researchers. The papers in these proceedings span a wide spectrum of areas in pow- aware systems. We have grouped the papers into the following categories: (1) microarchitecture- and circuit-level techniques, (2) power-aware memory and interconnect systems, and (3) frequency- and voltage-scaling techniques. The ?rst paper in the microarchitecture group proposes banking and wri- back ?ltering to reduce register ?le power. The second paper in this group - timizes both delay and power of the issue queue by packing two instructions in each issue queue entry and by memorizing upper-order bits of the wake-up tag. The third paper proposes bit slicing the datapath to exploit narrow width operations, and the last paper proposes to migrate application threads from one core to another in a multi-core chip to address thermal problems.

Welcome to the proceedings of the Power-Aware Computer Systems (PACS 2004) workshop held in conjunction with the 37th Annual International Sym- sium on Microarchitecture (MICRO-37). The continued increase of power and energy dissipation in computer systems has resulted in higher cost, lower re- ability, and reduced battery life in portable systems. Consequently, power and energy have become ?rst-class constraints at all layers of modern computer s- tems. PACS 2004 is the fourth workshop in its series to explore techniques to reduce power and energy at all levels of computer systems and brings together academic and industry researchers. The papers in these proceedings span a wide spectrum of areas in pow- aware systems. We have grouped the papers into the following categories: (1) microarchitecture- and circuit-level techniques, (2) power-aware memory and interconnect systems, and (3) frequency- and voltage-scaling techniques. The ?rst paper in the microarchitecture group proposes banking and wri- back ?ltering to reduce register ?le power. The second paper in this group - timizes both delay and power of the issue queue by packing two instructions in each issue queue entry and by memorizing upper-order bits of the wake-up tag. The third paper proposes bit slicing the datapath to exploit narrow width operations, and the last paper proposes to migrate application threads from one core to another in a multi-core chip to address thermal problems.

The phenomenal increases in computer system performance in recent years have been accompanied by a commensurate increase in power and energy dissipation. The latter has directly resulted in demand for expensive packaging and cooling technology, an increase in product cost, and a decrease in product reliability in all segments of the computing market. Moreover, the higher power/energy dissipation has signi cantly reduced battery life in portable systems. While - stem designers have traditionally relied on circuit-level techniques to reduce - wer/energy, there is a growing need to address power/energy dissipation at all levels of the computer system. We are pleased to welcome you to the proceedings of the Power-Aware C- puter Systems (PACS 2000) workshop. PACS 2000 was the rst workshop in its series and its aim was to bring together experts from academia and industry to address power-/energy-awareness at all levels of computer systems. In these p- ceedings, we bring you several excellent research contributions spanning a wide spectrum of areas in power-aware systems, from application all the way to c- pilers and microarchitecture, and to power/performance estimating models and tools. We have grouped the contributions into the following speci c categories: (1) power-aware microarchitectural/circuit techniques, (2) application/compiler power optimizations, (3) exploiting opportunity for power optimization in - struction scheduling and cache memories, and (4) power/performance models and tools.