Tsutomu Sasao – författare

Research and development of logic synthesis and verification have matured considerably over the last two decades of the 20th century. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges. This text provides a state-of-the-art view of logic synthesis and verification. It consists of 15 chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references. The book chapters are written by 28 recognized leaders in the field and reviewed by equally qualified experts; the topics collectively span the field. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field.

This text covers the basic topics of switching theory and logic synthesis in 14 chapters. Chapters one through five provide the mathematical foundation, while chapters six through eight include an introduction to sequential circuits, optimization of sequential machines and asynchronous sequential circuits. Chapters nine through fourteen are the main feature of the book. These chapters introduce and explain various topics that make up the subject of logic synthesis; multi-valued input two-valued output function, logic design for PLDs/FPGAs, EXOR-based design, and complexity theories of logic networks. An appendix providing a history of switching theory is included. The reference list consists of over four hundred entries. It is based on the author's lectures at Kyushu Institute of technology as well as seminars for CAD engineers from various Japanese technology companies.

"Logic Synthesis and Optimization" presents up-to-date research information in a pedagogical form. The authors are recognized as the leading experts on the subject. The focus of this book is on logic minimization and includes such topics as two-level minimization, multi-level minimization, application of binary decision diagrams, delay optimization, asynchronous circuits, spectral method for logic design, field programmable gate array (FPGA) design, EXOR logic synthesis and technology mapping. Examples and illustrations are included so that each contribution can be read independently. "Logic Synthesis and Optimization" is an indispensable reference for academic researchers as well as professional CAD engineers.

This is an edited volume containing 13 chapter contributions from leading researchers, with a focus on the latest research results. The first three chapters are introductions and contain many illustrations to clarify concepts presented in the text. It is recommended that these chapters are read first. The book then deals with the following topics: binary decision diagrams (BDDs); multi-terminal binary decision diagrams (MTBDDs); edge-valued binary decision diagrams (EVBDDs); functional decision diagrams (FDDs); Kronecker decision diagrams (KDDs); binary moment diagrams (BMDs); spectral transform decision diagrams (STDDs); ternary decision diagrams (TDDs); spectral transformation of logic functions; other transformations of logic functions; EXOR-based two-level expressions; FPRM minimization with TDDs and MTBDDs; complexity theories on FDDs; multi-level logic synthesis; and complexity of three-level logic networks. The book is designed for CAD researchers and engineers and should also be of interest to computer scientists who are interested in combinatorial problems. Exercises prepared by the editors help make this book useful as a graduate-level textbook.

This book describes the synthesis of logic functions using memories. It is useful to design field programmable gate arrays (FPGAs) that contain both small-scale memories, called look-up tables (LUTs), and medium-scale memories, called embedded memories. This is a valuable reference for both FPGA system designers and CAD tool developers, concerned with logic synthesis for FPGAs.

Representations of Discrete Functions is an edited volume containing 13 chapter contributions from leading researchers with a focus on the latest research results. The first three chapters are introductions and contain many illustrations to clarify concepts presented in the text. It is recommended that these chapters are read first. The book then deals with the following topics: binary decision diagrams (BDDs), multi-terminal binary decision diagrams (MTBDDs), edge-valued binary decision diagrams (EVBDDs), functional decision diagrams (FDDs), Kronecker decision diagrams (KDDs), binary moment diagrams (BMDs), spectral transform decision diagrams (STDDs), ternary decision diagrams (TDDs), spectral transformation of logic functions, other transformations oflogic functions, EXOR-based two-level expressions, FPRM minimization with TDDs and MTBDDs, complexity theories on FDDs, multi-level logic synthesis, and complexity of three-level logic networks. Representations of Discrete Functions is designed for CAD researchers and engineers and will also be of interest to computer scientists who are interested in combinatorial problems. Exercises prepared by the editors help make this book useful as a graduate level textbook.

Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges. Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references. Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field. Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools. From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc.

Logic Synthesis and Optimization presents up-to-date research information in a pedagogical form. The authors are recognized as the leading experts on the subject. The focus of the book is on logic minimization and includes such topics as two-level minimization, multi-level minimization, application of binary decision diagrams, delay optimization, asynchronous circuits, spectral method for logic design, field programmable gate array (FPGA) design, EXOR logic synthesis and technology mapping. Examples and illustrations are included so that each contribution can be read independently. Logic Synthesis and Optimization is an indispensable reference for academic researchers as well as professional CAD engineers.

Switching Theory for Logic Synthesis covers the basic topics of switching theory and logic synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation. Chapters 6 through 8 include an introduction to sequential circuits, optimization of sequential machines and asynchronous sequential circuits. Chapters 9 through 14 are the main feature of the book. These chapters introduce and explain various topics that make up the subject of logic synthesis: multi-valued input two-valued output function, logic design for PLDs/FPGAs, EXOR-based design, and complexity theories of logic networks. An appendix providing a history of switching theory is included. The reference list consists of over four hundred entries. Switching Theory for Logic Synthesis is based on the author's lectures at Kyushu Institute of Technology as well as seminars for CAD engineers from various Japanese technology companies. Switching Theory for Logic Synthesis will be of interest to CAD professionals and students at the advanced level. It is also useful as a textbook, as each chapter contains examples, illustrations, and exercises.

This book describes the synthesis of logic functions using memories. It is useful to design field programmable gate arrays (FPGAs) that contain both small-scale memories, called look-up tables (LUTs), and medium-scale memories, called embedded memories. This is a valuable reference for both FPGA system designers and CAD tool developers, concerned with logic synthesis for FPGAs.

In the case of hardware implementation, circuit design can employ look-up tables (memory), rather than threshold gates. The methodology described in this book involves extracting a set of rules from a training set, composed of categorical variable vectors and their corresponding classes.

In the case of hardware implementation, circuit design can employ look-up tables (memory), rather than threshold gates. The methodology described in this book involves extracting a set of rules from a training set, composed of categorical variable vectors and their corresponding classes.

Table of Contents: Equivalence Classes of Boolean Functions / Boolean Functions for Cryptography / Boolean Differential Calculus / Synthesis of Boolean Functions in Reversible Logic / Data Mining Using Binary Decision Diagrams

A zero-suppressed decision diagram (ZDD) is a data structure to represent objects that typically contain many zeros. Applications include combinatorial problems, such as graphs, circuits, faults, and data mining. This book consists of four chapters on the applications of ZDDs. The first chapter by Alan Mishchenko introduces the ZDD. It compares ZDDs to BDDs, showing why a more compact representation is usually achieved in a ZDD. The focus is on sets of subsets and on sum-of-products (SOP) expressions. Methods to generate all the prime implicants (PIs), and to generate irredundant SOPs are shown. A list of papers on the applications of ZDDs is also presented. In the appendix, ZDD procedures in the CUDD package are described. The second chapter by Tsutomu Sasao shows methods to generate PIs and irredundant SOPs using a divide and conquer method. This chapter helps the reader to understand the methods presented in the first chapter. The third chapter by Shin-Ichi Minato introduces the ""frontier-based"" method that efficiently enumerates certain subsets of a graph. The final chapter by Shinobu Nagayama shows a method to match strings of characters. This is important in routers, for example, where one must match the address information of an internet packet to the proprer output port. It shows that ZDDs are more compact than BDDs in solving this important problem. Each chapter contains exercises, and the appendix contains their solutions. Table of Contents: Preface / Acknowledgments / Introduction to Zero-Suppressed Decision Diagrams / Efficient Generation of Prime Implicants and Irredundant Sum-of-Products Expressions / The Power of Enumeration--BDD/ZDD-Based Algorithms for Tackling Combinatorial Explosion / Regular Expression Matching Using Zero-Suppressed Decision Diagrams / Authors' and Editors' Biographies / Index