Laurence Pierre – författare

CHARME’99 is the tenth in a series of working conferences devoted to the dev- opment and use of leading-edge formal techniques and tools for the design and veri?cation of hardware and systems. Previous conferences have been held in Darmstadt (1984), Edinburgh (1985), Grenoble (1986), Glasgow (1988), Leuven (1989), Torino (1991), Arles (1993), Frankfurt (1995) and Montreal (1997). This workshop and conference series has been organized in cooperation with IFIP WG 10. 5. It is now the biannual counterpart of FMCAD, which takes place every even-numbered year in the USA. The 1999 event took place in Bad Her- nalb, a resort village located in the Black Forest close to the city of Karlsruhe. The validation of functional and timing behavior is a major bottleneck in current VLSI design systems. A predominantly academic area of study until a few years ago, formal design and veri?cation techniques are now migrating into industrial use. The aim of CHARME’99 is to bring together researchers and users from academia and industry working in this active area of research. Two invited talks illustrate major current trends: the presentation by G´erard Berry (Ecole des Mines de Paris, Sophia-Antipolis, France) is concerned with the use of synchronous languages in circuit design, and the talk given by Peter Jansen (BMW, Munich, Germany) demonstrates an application of formal methods in an industrial environment. The program also includes 20 regular presentations and 12 short presentations/poster exhibitions that have been selected from the 48 submitted papers.

These proceedings contain the papers presented at theAdvanced Research Working Conference on Correct HardwareDesign Methodologies, held in Arles, France, in May 1993,and organized by the ESPRIT Working Group 6018 CHARME-2andthe Universit de Provence, Marseille, in cooperation withIFIP Working Group 10.2.Formal verification is emerging as a plausible alternativeto exhaustive simulation for establishing correct digitalhardware designs. The validation of functional and timingbehavior is a major bottleneck in current VLSI designsystems, slowing the arrival of products in the marketplacewith its associated increase in cost. From being apredominantly academic area of study until a few years ago,formal design and verification techniques are now beginningto migrate into industrial use. As we are now witnessing anincrease in activity in this area in both academia andindustry, the aim of this working conference was to bringtogether researchers and users from both communities.