Mohammed Ismail - Böcker

Adaptive Techniques for Mixed Signal Sytem on Chip discusses the concept of adaptation in the context of analog and mixed signal design along with different adaptive architectures used to control any system parameter. The first part of the book gives an overview of the different elements that are normally used in adaptive designs including tunable elements as well as voltage, current, and time references with an emphasis on the circuit design of specific blocks such as voltage-controlled transconductors, offset comparators, and a novel technique for accurate implementation of on chip resistors. While the first part of the book addresses adaptive techniques at the circuit and block levels, the second part discusses adaptive equalization architectures employed to minimize the impact of ISI (Intersymbol Interference) on the quality of received data in high-speed wire line transceivers. It presents the implementation of a 125Mbps transceiver operating over a variable length of Category 5 (CAT-5) Ethernet cable as an example of adaptive equalizers.

This volume focuses on the design procedure and the testing issues of CMOS RF power amplifiers, addressing RF CMOS power amplifier design for emerging wireless standards. The focus on power amplifiers for short distance wireless personal and local area networks (PAN and LAN), however the design techniques are also applicable to emerging wide area networks (WAN) infrastructure using micro or pico cell networks. The book discusses CMOS power amplifier design principles and theory and describes the architectures and tradeoffs in designing linear and nonlinear power amplifiers. It then details design examples of RF CMOS power amplifiers for short distance wireless applications (e, g., Bluetooth, WLAN) including designs for multi-standard platforms. Design aspects of RF circuits in deep submicron CMOS are also discussed. It should serve as a reference for RF IC design engineers and RD and R&D managers in industry, and for graduate students conducting research in wireless semiconductor IC design in general and with CMOS technology in particular.

This volume contains the proceedings of a workshop on Analog Integrated Neural Systems held May 8, 1989, in connection with the International Symposium on Circuits and Systems. The presentations were chosen to encompass the entire range of topics currently under study in this exciting new discipline. Stringent acceptance requirements were placed on contributions: (1) each description was required to include detailed characterization of a working chip, and (2) each design was not to have been published previously. In several cases, the status of the project was not known until a few weeks before the meeting date. As a result, some of the most recent innovative work in the field was presented. Because this discipline is evolving rapidly, each project is very much a work in progress. Authors were asked to devote considerable attention to the shortcomings of their designs, as well as to the notable successes they achieved. In this way, other workers can now avoid stumbling into the same traps, and evolution can proceed more rapidly (and less painfully). The chapters in this volume are presented in the same order as the corresponding presentations at the workshop. The first two chapters are concerned with fmding solutions to complex optimization problems under a predefmed set of constraints. The first chapter reports what is, to the best of our knowledge, the first neural-chip design. In each case, the physics of the underlying electronic medium is used to represent a cost function in a natural way, using only nearest-neighbor connectivity.

Very large scale integration (VLSI) technologies are now maturing with a current emphasis toward submicron structures and sophisticated applications combining digital as well as analog circuits on a single chip. Abundant examples are found on today's advanced systems for telecom­ munications, robotics, automotive electronics, image processing, intelli­ gent sensors, etc .. Exciting new applications are being unveiled in the field of neural computing where the massive use of analog/digital VLSI technologies will have a significant impact. To match such a fast technological trend towards single chip ana­ logi digital VLSI systems, researchers worldwide have long realized the vital need of producing advanced computer aided tools for designing both digital and analog circuits and systems for silicon integration. Ar­ chitecture and circuit compilation, device sizing and the layout genera­ tion are but a few familiar tasks on the world of digital integrated circuit design which can be efficiently accomplished by matured computer aided tools. In contrast, the art of tools for designing and producing analog or even analogi digital integrated circuits is quite primitive and still lack­ ing the industrial penetration and acceptance already achieved by digital counterparts. In fact, analog design is commonly perceived to be one of the most knowledge-intensive design tasks and analog circuits are still designed, largely by hand, by expert intimately familiar with nuances of the target application and integrated circuit fabrication process. The techniques needed to build good analog circuits seem to exist solely as expertise invested in individual designers.

As MOS devices are scaled to meet increasingly demanding circuit specifications, process variations have a greater effect on the reliability of circuit performance. For this reason, statistical techniques are required in order to design integrated circuits with maximum yield. "Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits" describes a statistical circuit simulation and optimization environment for VLSI circuit designers. The first step toward accomplishing statistical circuit design and optimization is the development of an accurate CAD tool capable of performing statistical simulation. This tool must be based on a statistical model which comprehends the effect of device and circuit characteristics, such as device size, bias, and circuit layout, which are under the control of the circuit designer on the variability of circuit performance. The distinctive feature of the CAD tool described in this book is its ability to accurately model and simulate the effect in both intra- and inter-die process variability on analogue/digital circuits, accounting for the effects of the aforementioned device and circuit characteristics."Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits" serves as an excellent reference for those working in the field, and may be used as the text for an advanced course on the subject.

This text discusses both single and two-stage architectures. Op amps with constant-GM input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-GM input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, The Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits is demonstrated. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in detail, so this book can be read by those without much experience in analog circuit design. It should be a useful reference book, and may be used as a text for advanced courses on the subject.

Radio Design in Nanometer Technologies addresses current trends and future directions in radio design for wireless applications. As radio transceivers constitute the major bottleneck in a wireless chipset in terms of power consumption and die size, the radio must be designed in the context of the entire system, end to end. Therefore the book will address wireless systems as well as the DSP parts before it gets into coverage of radio design issues. As such, the book is the first volume that looks at the integrated radio design problem as a "piece of a big puzzle", namely the entire chipset or single chip that builds an entire wireless system. This is the only way to successfully design radios to meet the stringent demands of today’s increasingly complex wireless systems.

Wireless communications is witnessing tremendous growth with proliferation of different standards covering wide, local and personal area networks (WAN, LAN and PAN). Contemporary trends call for designs that allow: smooth migration to future generations of wireless standards with higher data rates for multimedia applications; convergence of wireless services allowing access to different standards from the same wireless device; and cost effective design solutions for intercontinental roaming. This requires designs that work across multiple wireless standards, can easily be reused, achieve maximum hardware share at minimum power consumption levels particularly for mobile battery-operated devices. While serious efforts are underway to develop highly integrated solutions for digital basebands covering multiple standards, emerging multi-standard, multi-band wireless devices use "stacked" transceivers, that is, separate transceivers for different standards. This represents a major bottleneck in attempting to achieve higher levels of integration and reduce the bill of material for a multi-standard wireless device.Development of radio architectures and mixed-signal design solutions that support multiple standards is therefore needed. This is one of the main objectives of this book. It covers both the analysis and design aspects of CMOS radio receivers with primary focus on receivers for mobile terminals. The subject of multi-standard data converter design for base stations is also covered. The book also details a complete analysis of a multi-standard receiver chain from the antenna to the data converter establishing the design specifications of all blocks in both the radio and mixed-signal parts. The specifications are conveniently tabulated throughout the book and span a level of details from the noise figure and linearity requirements of RF blocks down to such circuit details as, for example, DC gain, settling behaviour, noise and matching requirements of amplifiers (OTAs) in the data converter.

Substrate noise coupling in integrated circuits (ICs) is the process by which int- ference signals in the form of voltage and current glitches cause parasitic currents to ?ow in the silicon substrate to various parts of the IC. The source of such glitches and parasitic currents could be from the switching noise of high speed digital clocks on the same chip. In RF and mixed signal ICs the switching noise is coupled to sensitive analog and RF nodes in the IC causing degradation in performance that could severely impact the yield. Thus, overcoming substrate coupling is a key issue in successful “system on chip” ?rst-pass integration where RF and mixed signal blocks, high speed digital I/O interface are integrated with digital signal proce- ing algorithms on the same chip. This is particularly true as we move to sub-90 nanometer system on chip integration. In this book a substrate aware design ?ow is built, calibrated to silicon and used as part of the design and validation ?ows to uncover and ?x substrate coupling problems in RF ICs. The ?ow is used to develop a comprehensive RF substrate noise isolation design guide to be used by RF designers during the ?oor planning, circuit design and validation phases. This will allow designers to optimize the - sign, maximize noise isolation and protect sensitive analog/RF blocks from being degraded by substrate noise coupling.

Adaptive Techniques for Mixed Signal Sytem on Chip discusses the concept of adaptation in the context of analog and mixed signal design along with different adaptive architectures used to control any system parameter. The first part of the book gives an overview of the different elements that are normally used in adaptive designs including tunable elements as well as voltage, current, and time references with an emphasis on the circuit design of specific blocks such as voltage-controlled transconductors, offset comparators, and a novel technique for accurate implementation of on chip resistors. While the first part of the book addresses adaptive techniques at the circuit and block levels, the second part discusses adaptive equalization architectures employed to minimize the impact of ISI (Intersymbol Interference) on the quality of received data in high-speed wire line transceivers. It presents the implementation of a 125Mbps transceiver operating over a variable length of Category 5 (CAT-5) Ethernet cable as an example of adaptive equalizers.

This book will introduce various power management integrated circuits (IC) design techniques to build future energy-efficient “green” electronics. The goal is to achieve high efficiency, which is essential to meet consumers’ growing need for longer battery lives. The focus is to study topologies amiable for full on-chip implementation (few external components) in the mainstream CMOS technology, which will reduce the physical size and the manufacturing cost of the devices.

This book will introduce design methodologies, known as Built-in-Self-Test (BiST) and Built-in-Self-Calibration (BiSC), which enhance the robustness of radio frequency (RF) and millimeter wave (mmWave) integrated circuits (ICs). These circuits are used in current and emerging communication, computing, multimedia and biomedical products and microchips. The design methodologies presented will result in enhancing the yield (percentage of working chips in a high volume run) of RF and mmWave ICs which will enable successful manufacturing of such microchips in high volume.

This book introduces the concept of voltage-controlled-oscillator (VCO)-based analog-to-digital converters (ADCs). Detailed explanation is given of this promising new class of high resolution and low power ADCs, which use time quantization as opposed to traditional analog-based (i.e. voltage) ADCs.

Very large scale integration (VLSI) technologies are now maturing with a current emphasis toward submicron structures and sophisticated applications combining digital as well as analog circuits on a single chip. Abundant examples are found on today's advanced systems for telecom­ munications, robotics, automotive electronics, image processing, intelli­ gent sensors, etc .. Exciting new applications are being unveiled in the field of neural computing where the massive use of analog/digital VLSI technologies will have a significant impact. To match such a fast technological trend towards single chip ana­ logi digital VLSI systems, researchers worldwide have long realized the vital need of producing advanced computer aided tools for designing both digital and analog circuits and systems for silicon integration. Ar­ chitecture and circuit compilation, device sizing and the layout genera­ tion are but a few familiar tasks on the world of digital integrated circuit design which can be efficiently accomplished by matured computer aided tools. In contrast, the art of tools for designing and producing analog or even analogi digital integrated circuits is quite primitive and still lack­ ing the industrial penetration and acceptance already achieved by digital counterparts. In fact, analog design is commonly perceived to be one of the most knowledge-intensive design tasks and analog circuits are still designed, largely by hand, by expert intimately familiar with nuances of the target application and integrated circuit fabrication process. The techniques needed to build good analog circuits seem to exist solely as expertise invested in individual designers.

This volume contains the proceedings of a workshop on Analog Integrated Neural Systems held May 8, 1989, in connection with the International Symposium on Circuits and Systems. The presentations were chosen to encompass the entire range of topics currently under study in this exciting new discipline. Stringent acceptance requirements were placed on contributions: (1) each description was required to include detailed characterization of a working chip, and (2) each design was not to have been published previously. In several cases, the status of the project was not known until a few weeks before the meeting date. As a result, some of the most recent innovative work in the field was presented. Because this discipline is evolving rapidly, each project is very much a work in progress. Authors were asked to devote considerable attention to the shortcomings of their designs, as well as to the notable successes they achieved. In this way, other workers can now avoid stumbling into the same traps, and evolution can proceed more rapidly (and less painfully). The chapters in this volume are presented in the same order as the corresponding presentations at the workshop. The first two chapters are concerned with fmding solutions to complex optimization problems under a predefmed set of constraints. The first chapter reports what is, to the best of our knowledge, the first neural-chip design. In each case, the physics of the underlying electronic medium is used to represent a cost function in a natural way, using only nearest-neighbor connectivity.

Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference book, and may be used as a text for advanced courses on the subject.

As MOS devices are scaled to meet increasingly demanding circuit specifications, process variations have a greater effect on the reliability of circuit performance. For this reason, statistical techniques are required to design integrated circuits with maximum yield. Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits describes a statistical circuit simulation and optimization environment for VLSI circuit designers. The first step toward accomplishing statistical circuit design and optimization is the development of an accurate CAD tool capable of performing statistical simulation. This tool must be based on a statistical model which comprehends the effect of device and circuit characteristics, such as device size, bias, and circuit layout, which are under the control of the circuit designer on the variability of circuit performance. The distinctive feature of the CAD tool described in this book is its ability to accurately model and simulate the effect in both intra- and inter-die process variability on analog/digital circuits, accounting for the effects of the aforementioned device and circuit characteristics. Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits serves as an excellent reference for those working in the field, and may be used as the text for an advanced course on the subject.

This book describes the design and implementation of an electronic subsystem called the frequency synthesizer, which is a very important building block for any wireless transceiver. The discussion includes several new techniques for the design of such a subsystem which include the usage modes of the wireless device, including its support for several leading-edge wireless standards. This new perspective for designing such a demanding subsystem is based on the fact that optimizing the performance of a complete system is not always achieved by optimizing the performance of its building blocks separately.  This book provides “hands-on” examples of this sort of co-design of optimized subsystems, which can make the vision of an always-best-connected scenario a reality.

This book will introduce various power management integrated circuits (IC) design techniques to build future energy-efficient “green” electronics. The goal is to achieve high efficiency, which is essential to meet consumers’ growing need for longer battery lives. The focus is to study topologies amiable for full on-chip implementation (few external components) in the mainstream CMOS technology, which will reduce the physical size and the manufacturing cost of the devices.

RF CMOS Power Amplifiers: Theory Design and Implementation focuses on the design procedure and the testing issues of CMOS RF power amplifiers. This is the first monograph addressing RF CMOS power amplifier design for emerging wireless standards. The focus on power amplifiers for short is distance wireless personal and local area networks (PAN and LAN), however the design techniques are also applicable to emerging wide area networks (WAN) infrastructure using micro or pico cell networks. The book discusses CMOS power amplifier design principles and theory and describes the architectures and tardeoffs in designing linear and nonlinear power amplifiers. It then details design examples of RF CMOS power amplifiers for short distance wireless applications (e, g., Bluetooth, WLAN) including designs for multi-standard platforms. Design aspects of RF circuits in deep submicron CMOS are also discussed. RF CMOS Power Amplifiers: Theory Design and Implementation serves as a reference for RF IC design engineers and RD and R&D managers in industry, and for graduate students conducting research in wireless semiconductor IC design in general and with CMOS technology in particular.

Multi-Standard CMOS Wireless Receivers: Analysis and Design is the first book on the subject of multi-standard wireless receivers. It covers both the analysis and design aspects of CMOS radio receivers with primary focus on receivers for mobile terminals. The subject of multi-standard data converter design for base stations is also covered. The book is the first to detail a complete analysis of a multi-standard receiver chain from the antenna to the data converter establishing the design specifications of all blocks in both the radio and mixed-signal parts. The specifications are conveniently tabulated throughout the book and span a level of details from the noise figure and linearity requirements of RF blocks down to such circuit details as, e.g., DC gain, settling behavior, noise and matching requirements of amplifiers (OTAs) in the data converter.Multi-Standard CMOS Wireless Receivers: Analysis and Design serves as a reference for RF IC and mixed-signal designers, wireless receiver system designers, design managers and project leaders in industry, particularly those in the wireless semiconductor industry.

CMOS PLLs and VCOs for 4G Wireless is the first book devoted to the subject of CMOS PLL and VCO design for future broadband 4th generation wireless devices. These devices will be handheld-centric, requiring very low power consumption and small footprint. They will be able to work across multiple bands and multiple standards covering WWAN (GSM,WCDMA) ,WLAN(802.11 a/b/g) and WPAN(Bluetooth) with different modulations, channel bandwidths , phase noise requirements ,etc. As such, this book discusses design, modeling and optimization techniques for low power fully integrated broadband PLLs and VCOs in deep submicron CMOS. First, the PLL and VCO performances are studied in the context of the chosen multi-band multi-standard, radio architecture and the adopted frequency plan. Next a thorough study of the design requirements for broadband PLL/VCO design is conducted together with modeling techniques for noise sources in a PLL and VCO focusing on optimization of integrated phase noise for multi-carrier OFDM 64-QAM type applications. Design examples for multi-standard 802.111a/b/g as well as for GSM/WCDMA are fully described and experimental results from 0.18 micron CMOS test chips have demonstrated the validity of the proposed design and optimization techniques. Equally important the work describes techniques for robust high volume production of RF radios in general and for integrated PLL/VCO design in particular including issues such as supply sensitivity, ground bounce and calibration mechanisms. CMOS PLLS and VCOs for 4G Wireless will be of interest to graduate students in electrical and computer engineering, design managers and RFIC designers in wireless semiconductor companies.

This book describes the design and implementation of an electronic subsystem called the frequency synthesizer, which is a very important building block for any wireless transceiver. The discussion includes several new techniques for the design of such a subsystem which include the usage modes of the wireless device, including its support for several leading-edge wireless standards. This new perspective for designing such a demanding subsystem is based on the fact that optimizing the performance of a complete system is not always achieved by optimizing the performance of its building blocks separately.  This book provides “hands-on” examples of this sort of co-design of optimized subsystems, which can make the vision of an always-best-connected scenario a reality.

This book documents some of the most recent advances on the physical layer of the Internet of Things (IoT), including sensors, circuits, and systems. The book is unique in that it adopts a holistic view of such systems and includes not only the sensor and processing subsystems, but also the power, communication, and security subsystems.

​This book describes an ECG processing architecture that guides biomedical SoC developers, from theory to implementation and testing. The authors provide complete coverage of the digital circuit implementation of an ultra-low power biomedical SoC,  comprised of a detailed description of an ECG processor implemented and fabricated on chip.  Coverage also includes the challenges and tradeoffs of designing ECG processors.Describes digital circuit architecture for implementing ECG processing algorithms on chip;Includes coverage of signal processing techniques for ECG processing;Features ultra-low power circuit design techniques;Enables design of ECG processing architectures and their respective on-chip implementation.

This book describes power management integrated circuits (PMIC), for power converters and voltage regulators necessary for energy efficient and small form factor systems. The authors discuss state-of-the-art PMICs not only for battery powered wearable devices, but also energy harvesting-based devices. The circuits presented support voltage scaling to reduce the overall average power consumption of a wearable device, resulting in longer device operating time. The discussion includes many designs, control techniques and approaches to distribute efficiently the power among different blocks in the device.•Demonstrates for readers how to innovate in designing power management integrated circuits (PMIC) suitable for wearable devices, powered by either battery or harvesting energy;•Introduces a dual outputs switched capacitor, using a single voltage regulator to minimize the area overhead and discusses the effect of having more than two outputs on the area and power efficiency;•Introduces a novel clock-less digital LDO regulator that eliminates the use of the clocked comparator and serial shift register in the conventional design;•Presents experimental results of energy harvesting-based power management units (PMU), using different combinations of power converters and voltage regulators, providing a guide for designers to select the appropriate option based on device requirements.

This book describes power management integrated circuits (PMIC), for power converters and voltage regulators necessary for energy efficient and small form factor systems. The authors discuss state-of-the-art PMICs not only for battery powered wearable devices, but also energy harvesting-based devices. The circuits presented support voltage scaling to reduce the overall average power consumption of a wearable device, resulting in longer device operating time. The discussion includes many designs, control techniques and approaches to distribute efficiently the power among different blocks in the device.•Demonstrates for readers how to innovate in designing power management integrated circuits (PMIC) suitable for wearable devices, powered by either battery or harvesting energy;•Introduces a dual outputs switched capacitor, using a single voltage regulator to minimize the area overhead and discusses the effect of having more than two outputs on the area and power efficiency;•Introduces a novel clock-less digital LDO regulator that eliminates the use of the clocked comparator and serial shift register in the conventional design;•Presents experimental results of energy harvesting-based power management units (PMU), using different combinations of power converters and voltage regulators, providing a guide for designers to select the appropriate option based on device requirements.

This book introduces power amplifier design in 22nm FDSOI CMOS dedicated towards 5G applications at 28 GHz and presents 4 state-of-the-art power amplifier designs. The authors discuss power amplifier performance metrics, design trade-offs, and presents different power amplifier classes utilizing efficiency enhancement techniques at 28 GHz.

This book introduces power amplifier design in 22nm FDSOI CMOS dedicated towards 5G applications at 28 GHz and presents 4 state-of-the-art power amplifier designs. The authors discuss power amplifier performance metrics, design trade-offs, and presents different power amplifier classes utilizing efficiency enhancement techniques at 28 GHz.