Ramesh Harjani – författare

This book focuses on high performance radio frequency integrated circuits (RF IC) design in CMOS. 1. Development of radio frequency ICs Wireless communications has been advancing rapidly in the past two decades. Many high performance systems have been developed, such as cellular systems (AMPS, GSM, TDMA, CDMA, W-CDMA, etc. ), GPS system (global po- tioning system) and WLAN (wireless local area network) systems. The rapid growth of VLSI technology in both digital circuits and analog circuits provides benefits for wireless communication systems. Twenty years ago not many p- ple could imagine millions of transistors in a single chip or a complete radio for size of a penny. Now not only complete radios have been put in a single chip, but also more and more functions have been realized by a single chip and at a much lower price. A radio transmits and receives electro-magnetic signals through the air. The signals are usually transmitted on high frequency carriers. For example, a t- ical voice signal requires only 30 Kilohertz bandwidth. When it is transmitted by a FM radio station, it is often carried by a frequency in the range of tens of megahertz to hundreds of megahertz. Usually a radio is categorized by its carrier frequency, such as 900 MHz radio or 5 GHz radio. In general, the higher the carrier frequency, the better the directivity, but the more difficult the radio design.

Oversampled A/D converters have become very popular in recent years. Some of their advantages include relaxed requirements for anti-alias filters, relaxed requirements for component matching, high resolution and compatibility with digital VLSI technology. There is a significant amount of literature discussing the principle, theory and implementation of various oversampled converters. Such converters are likely to continue to proliferate in the foreseeable future. Additionally, more recently there has been great interest in low voltage and low power circuit design. New design techniques have been proposed for both the digital domain and the analog domain. Both trends point to the importance of the low-power design of oversampled A/D converters. Unfortunately, there has been no systematic study of the optimal design of modulators for oversampled converters. Design has generally focused on new architectures with little attention being paid to optimization. The goal of Design of Modulators for Oversampled Converters is to develop a methodology for the optimal design of modulators in oversampled converters. The primary focus of the presentation is on minimizing power consumption and understanding and limiting the nonlinearities that result in such converters. Design of Modulators for Oversampled Converters offers a quantitative justification for the various design tradeoffs and serves as a guide for designing low-power highly linear oversampled converters. Design of Modulators for Oversampled Converters will serve as a valuable guide for circuit design practitioners, university researchers and graduate students who are interested in this fast-moving area.

Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results.The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.

This book focuses on high performance radio frequency integrated circuits (RF IC) design in CMOS. 1. Development of radio frequency ICs Wireless communications has been advancing rapidly in the past two decades. Many high performance systems have been developed, such as cellular systems (AMPS, GSM, TDMA, CDMA, W-CDMA, etc. ), GPS system (global po- tioning system) and WLAN (wireless local area network) systems. The rapid growth of VLSI technology in both digital circuits and analog circuits provides benefits for wireless communication systems. Twenty years ago not many p- ple could imagine millions of transistors in a single chip or a complete radio for size of a penny. Now not only complete radios have been put in a single chip, but also more and more functions have been realized by a single chip and at a much lower price. A radio transmits and receives electro-magnetic signals through the air. The signals are usually transmitted on high frequency carriers. For example, a t- ical voice signal requires only 30 Kilohertz bandwidth. When it is transmitted by a FM radio station, it is often carried by a frequency in the range of tens of megahertz to hundreds of megahertz. Usually a radio is categorized by its carrier frequency, such as 900 MHz radio or 5 GHz radio. In general, the higher the carrier frequency, the better the directivity, but the more difficult the radio design.

Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results.The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.

Oversampled A/D converters have become very popular in recent years. Some of their advantages include relaxed requirements for anti-alias filters, relaxed requirements for component matching, high resolution and compatibility with digital VLSI technology. There is a significant amount of literature discussing the principle, theory and implementation of various oversampled converters. Such converters are likely to continue to proliferate in the foreseeable future. Additionally, more recently there has been great interest in low voltage and low power circuit design. New design techniques have been proposed for both the digital domain and the analog domain. Both trends point to the importance of the low-power design of oversampled A/D converters. Unfortunately, there has been no systematic study of the optimal design of modulators for oversampled converters. Design has generally focused on new architectures with little attention being paid to optimization. The goal of Design of Modulators for Oversampled Converters is to develop a methodology for the optimal design of modulators in oversampled converters. The primary focus of the presentation is on minimizing power consumption and understanding and limiting the nonlinearities that result in such converters. Design of Modulators for Oversampled Converters offers a quantitative justification for the various design tradeoffs and serves as a guide for designing low-power highly linear oversampled converters. Design of Modulators for Oversampled Converters will serve as a valuable guide for circuit design practitioners, university researchers and graduate students who are interested in this fast-moving area.

This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures.

This book focuses on the architecture and circuit design for cognitive radio receiver front-ends. The authors first provide a holistic explanation of RF circuits for cognitive radio systems. This is followed by an in-depth exploration of existing techniques that can be utilized by circuit designers. Coverage also includes novel circuit techniques and architectures that can be invaluable for designers for cognitive radio systems.

This book focuses on the architecture and circuit design for cognitive radio receiver front-ends. The authors first provide a holistic explanation of RF circuits for cognitive radio systems. This is followed by an in-depth exploration of existing techniques that can be utilized by circuit designers. Coverage also includes novel circuit techniques and architectures that can be invaluable for designers for cognitive radio systems.

This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures.

This book describes novel and disruptive architecture and circuit design techniques, toward the realization of low-power, standard-compliant radio architectures and silicon implementation of the circuits required for a variety of leading-edge applications.  Readers will gain an understanding of the circuit level challenges that exist for low power radios, compatible with the IEEE 802.15.6 standard. The authors discuss current techniques to address some of these challenges, helping readers to understand the state-of-the-art, and to address the various, open research problems that exist with respect to realizing low power radios.Enables readers to face challenging bottleneck in low power radio design, with state-of-the-art, circuit-level design techniques;Provides readers with basic knowledge of circuits suitable for low power radio circuits compatible with the IEEE 802.15.6 standard;Discusses new and emerging architectures and circuit techniques, enabling applications such as body area networks and internet of things.

This book describes novel and disruptive architecture and circuit design techniques, toward the realization of low-power, standard-compliant radio architectures and silicon implementation of the circuits required for a variety of leading-edge applications.  Readers will gain an understanding of the circuit level challenges that exist for low power radios, compatible with the IEEE 802.15.6 standard. The authors discuss current techniques to address some of these challenges, helping readers to understand the state-of-the-art, and to address the various, open research problems that exist with respect to realizing low power radios.Enables readers to face challenging bottleneck in low power radio design, with state-of-the-art, circuit-level design techniques;Provides readers with basic knowledge of circuits suitable for low power radio circuits compatible with the IEEE 802.15.6 standard;Discusses new and emerging architectures and circuit techniques, enabling applications such as body area networks and internet of things.

This book describes design techniques for wideband quadrature LO generation for software defined radio transceivers, with frequencies spanning 4GHz to around 80GHz. The authors discuss several techniques that can be used to reduce the cost and/or power consumption of one of the key component of the RF front-end, the quadrature local oscillator.  The discussion includes simple and useful insights into quadrature VCOs, along with numerous examples of practical techniques.

This book describes design techniques for wideband quadrature LO generation for software defined radio transceivers, with frequencies spanning 4GHz to around 80GHz. The authors discuss several techniques that can be used to reduce the cost and/or power consumption of one of the key component of the RF front-end, the quadrature local oscillator.  The discussion includes simple and useful insights into quadrature VCOs, along with numerous examples of practical techniques.

This book describes intuitive analog design approaches using digital inverters, providing filter architectures and circuit techniques enabling high performance analog circuit design. The authors provide process, supply voltage and temperature (PVT) variation-tolerant design techniques for inverter based circuits. They also discuss various analog design techniques for lower technology nodes and lower power supply, which can be used for designing high performance systems-on-chip.

This book describes intuitive analog design approaches using digital inverters, providing filter architectures and circuit techniques enabling high performance analog circuit design.