Santanu Chattopadhyay – författare

This book aims to highlight the research activities in the domain of thermal-aware testing. Thermal-aware testing can be employed both at circuit level and at system levelDescribes range of algorithms for addressing thermal-aware test issue, presents comparison of temperature reduction with power-aware techniques and include results on benchmark circuits and systems for different techniquesThis book will be suitable for researchers working on power- and thermal-aware design and the testing of digital VLSI chips

This book aims to highlight the research activities in the domain of thermal-aware testing. Thermal-aware testing can be employed both at circuit level and at system levelDescribes range of algorithms for addressing thermal-aware test issue, presents comparison of temperature reduction with power-aware techniques and include results on benchmark circuits and systems for different techniquesThis book will be suitable for researchers working on power- and thermal-aware design and the testing of digital VLSI chips

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integrationexamines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends.Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challengesNoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfacesThe router design strategies followed in NoCsThe evaluation mechanism of NoC architecturesThe application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCsThe signal integrity and reliability issues of NoCThe details of NoC testing strategies reported so farThe problem of synthesizing application-specific NoCsReconfigurable NoC design issuesDirection of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integrationcovers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integrationexamines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends.Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challengesNoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfacesThe router design strategies followed in NoCsThe evaluation mechanism of NoC architecturesThe application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCsThe signal integrity and reliability issues of NoCThe details of NoC testing strategies reported so farThe problem of synthesizing application-specific NoCsReconfigurable NoC design issuesDirection of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integrationcovers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.

This book constitutes the refereed proceedings of the 16th International Symposium on VSLI Design and Test, VDAT 2012, held in Shibpur, India, in July 2012.The 30 revised regular papers presented together with 10 short papers and 13 poster sessions were carefully selected from 135 submissions. The papers are organized in topical sections on VLSI design, design and modeling of digital circuits and systems, testing and verification, design for testability, testing memories and regular logic arrays, embedded systems: hardware/software co-design and verification, emerging technology: nanoscale computing and nanotechnology.