Sasan Iman - Böcker

This volume presents a systematic and comprehensive treatment of power modelling and optimization at the logic level. More precisely, it provides a detailed presentation of methodologies, algorithms and CAD tools for power modelling, estimation and analysis, synthesis and optimization at the logic level. The book contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. It is designed for engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

This book provides a detailed coverage of the e-hardware verification language (HVL), state of the art in verification methodologies, and the use of eHVL as a facilitating verification tool in implementing a state of the art verification environment. To this end, the book provides a comprehensive description of the new concepts introduced by the e language, e language syntax, and its associated semantics. In addition, the book describes architectural views and requirements of verification environments (i.e. randomly generated environments, coverage driven verification environments, etc.). Verification blocks in the architectural views (i.e. Generators, Initiators, Collectors, Checkers, Monitors, Coverage Definitions, etc.) and their implementations using the eHVL are also discussed in detail in separate parts of the book. The book describes the eReuse Methodology (RM), the motivation for defining such a guideline and step-by-step instructions for building an eRM compliant e Verification Component (eVC). A complete implementation of a UART eRM compliant eVC is used as the working example for putting all topics in perspective.This book is useful for a range of users, including junior verification engineers looking to learn just enough basic concepts and related syntax to get a head start on their project, advance users looking to enhance the effectiveness and quality of a verification environment, developers working to build e Verification Components and finally as reference for looking up specific information about a verification concept and its implementation using the eHVL.

Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.