Designer's Guide Book Series – serie

This is a book for engineers concerned with jitter: the e ects of noise visible in the time domain. The material presented will be helpful for work at both the system level and the circuit level: At the system level, the challenge is to describe, specify, and measure time domain uncertainty and when necessary, relate jitter to phase noise speci cations in the frequency domain. At the circuit level, the challenge is to design low noise circuitry within power, area, and process constraints so that ultimate performance meets system level requirements. Throughout the book concepts are presented in the context of an - gineering application requiring low jitter performance: the voltage controlled oscillator (VCO) used in a phase-locked loop (PLL). Techniques are presented for circuit-level design of low jitter delay elements for use in ring oscillators, as well as relating the circuit-level characteristics to system-level performance. Although the emphasis is on time-domain (jitter) measures of oscillator p- formance, a simple method of translating performance to frequency domain (phase noise) measures is presented as well. Structure of this Book This book is divided into nine chapters. The diagram on the following page shows the relationship between material in each chapter as well as placement in the system-level vs. circuit-level design hierarchy. Wherever possible, - perimental veri cation is presented in the same chapter as the corresponding theoretical development, rather than being isolated in a separate chapter.

Engineering productivity in integrated circuit product design and - velopment today is limited largely by the effectiveness of the CAD tools used. For those domains of product design that are highly dependent on transistor-level circuit design and optimization, such as high-speed logic and memory, mixed-signal analog-digital int- faces, RF functions, power integrated circuits, and so forth, circuit simulation is perhaps the single most important tool. As the complexity and performance of integrated electronic systems has increased with scaling of technology feature size, the capabilities and sophistication of the underlying circuit simulation tools have correspondingly increased. The absolute size of circuits requiring transistor-level simulation has increased dramatically, creating not only problems of computing power resources but also problems of task organization, complexity management, output representation, initial condition setup, and so forth. Also, as circuits of more c- plexity and mixed types of functionality are attacked with simu- tion, the spread between time constants or event time scales within the circuit has tended to become wider, requiring new strategies in simulators to deal with large time constant spreads.

try to predict it using mathematical expressions. His heuristic model without mathematical proof is almost universally accepted. However, it entails a c- cuit specific noise factor that is not known a priori and so is not predictive. In this work, we attempt to address the topic of oscillator design from a diff- ent perspective. By introducing a new paradigm that accurately captures the subtleties of phase noise we try to answer the question: 'why do oscillators behave in a particular way?' and 'what can be done to build an optimum design?' It is also hoped that the paradigm is useful in other areas of circuit design such as frequency synthesis and clock recovery. In Chapter 1, a general introduction and motivation to the subject is presented. Chapter 2 summarizes the fundamentals of phase noise and timing jitter and discusses earlier works on oscillator's phase noise analysis. Chapter 3 and Chapter 4 analyze the physical mechanisms behind phase noise generation in current-biased and Colpitts oscillators. Chapter 5 discusses design trade-offs and new techniques in LC oscillator design that allows optimal design. Chapter 6 and Chapter 7 discuss a topic that is typically ignored in oscillator design. That is flicker noise in LC oscillators. Finally, Chapter 8 is dedicated to the complete analysis of the role of varactors both in tuning and AM-FM noise conversion.

The Verilog Hardware Description Language (Verilog-HDL) has long been the most popular language for describing complex digital hardware. It started life as a prop- etary language but was donated by Cadence Design Systems to the design community to serve as the basis of an open standard. That standard was formalized in 1995 by the IEEE in standard 1364-1995. About that same time a group named Analog Verilog International formed with the intent of proposing extensions to Verilog to support analog and mixed-signal simulation. The first fruits of the labor of that group became available in 1996 when the language definition of Verilog-A was released. Verilog-A was not intended to work directly with Verilog-HDL. Rather it was a language with Similar syntax and related semantics that was intended to model analog systems and be compatible with SPICE-class circuit simulation engines. The first implementation of Verilog-A soon followed: a version from Cadence that ran on their Spectre circuit simulator. As more implementations of Verilog-A became available, the group defining the a- log and mixed-signal extensions to Verilog continued their work, releasing the defi- tion of Verilog-AMS in 2000. Verilog-AMS combines both Verilog-HDL and Verilog-A, and adds additional mixed-signal constructs, providing a hardware description language suitable for analog, digital, and mixed-signal systems. Again, Cadence was first to release an implementation of this new language, in a product named AMS Designer that combines their Verilog and Spectre simulation engines.

This is a book for engineers concerned with jitter: the e ects of noise visible in the time domain. The material presented will be helpful for work at both the system level and the circuit level: At the system level, the challenge is to describe, specify, and measure time domain uncertainty and when necessary, relate jitter to phase noise speci cations in the frequency domain. At the circuit level, the challenge is to design low noise circuitry within power, area, and process constraints so that ultimate performance meets system level requirements. Throughout the book concepts are presented in the context of an - gineering application requiring low jitter performance: the voltage controlled oscillator (VCO) used in a phase-locked loop (PLL). Techniques are presented for circuit-level design of low jitter delay elements for use in ring oscillators, as well as relating the circuit-level characteristics to system-level performance. Although the emphasis is on time-domain (jitter) measures of oscillator p- formance, a simple method of translating performance to frequency domain (phase noise) measures is presented as well. Structure of this Book This book is divided into nine chapters. The diagram on the following page shows the relationship between material in each chapter as well as placement in the system-level vs. circuit-level design hierarchy. Wherever possible, - perimental veri cation is presented in the same chapter as the corresponding theoretical development, rather than being isolated in a separate chapter.

try to predict it using mathematical expressions. His heuristic model without mathematical proof is almost universally accepted. However, it entails a c- cuit specific noise factor that is not known a priori and so is not predictive. In this work, we attempt to address the topic of oscillator design from a diff- ent perspective. By introducing a new paradigm that accurately captures the subtleties of phase noise we try to answer the question: 'why do oscillators behave in a particular way?' and 'what can be done to build an optimum design?' It is also hoped that the paradigm is useful in other areas of circuit design such as frequency synthesis and clock recovery. In Chapter 1, a general introduction and motivation to the subject is presented. Chapter 2 summarizes the fundamentals of phase noise and timing jitter and discusses earlier works on oscillator's phase noise analysis. Chapter 3 and Chapter 4 analyze the physical mechanisms behind phase noise generation in current-biased and Colpitts oscillators. Chapter 5 discusses design trade-offs and new techniques in LC oscillator design that allows optimal design. Chapter 6 and Chapter 7 discuss a topic that is typically ignored in oscillator design. That is flicker noise in LC oscillators. Finally, Chapter 8 is dedicated to the complete analysis of the role of varactors both in tuning and AM-FM noise conversion.

Engineering productivity in integrated circuit product design and - velopment today is limited largely by the effectiveness of the CAD tools used. For those domains of product design that are highly dependent on transistor-level circuit design and optimization, such as high-speed logic and memory, mixed-signal analog-digital int- faces, RF functions, power integrated circuits, and so forth, circuit simulation is perhaps the single most important tool. As the complexity and performance of integrated electronic systems has increased with scaling of technology feature size, the capabilities and sophistication of the underlying circuit simulation tools have correspondingly increased. The absolute size of circuits requiring transistor-level simulation has increased dramatically, creating not only problems of computing power resources but also problems of task organization, complexity management, output representation, initial condition setup, and so forth. Also, as circuits of more c- plexity and mixed types of functionality are attacked with simu- tion, the spread between time constants or event time scales within the circuit has tended to become wider, requiring new strategies in simulators to deal with large time constant spreads.