This book focusses on the spacer engineering aspects of novel MOS-based device–circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.
Sudeb Dasgupta, Brajesh Kumar Kaushik, Pankaj Kumar Pal
Innehållsförteckning
PrefaceAbout the AuthorsChapter 1 ◾ Introduction to NanoelectronicsChapter 2 ◾ Tri-Gate FinFET Technology and Its AdvancementChapter 3 ◾ Dual-k Spacer Device Architecture and Its ElectrostaticsChapter 4 ◾ Capacitive Analysis and Dual-k FinFET-Based Digital Circuit DesignChapter 5 ◾ Design Metric Improvement of a Dual-k–Based SRAM CellChapter 6 ◾ Statistical Variability and Sensitivity AnalysisINDEX