Dr Neha Singh is a well-rounded and dynamic teaching professional with 20+ years of in-depth experience in educating undergraduate and postgraduate engineering students in Electronics & Communication Engineering. She is currently working as Assistant Professor, in the Department of Electronics & Communication Engineering at Manipal University Jaipur, Rajasthan, India. She did her PhD in the year 2020. Her areas of research interest include Image Processing, Machine learning, VLSI design and nanodevices. She has several papers and book chapters published in Journals, books and conferences of repute. She has co-authored engineering textbooks and edited three Scopus indexed books on Nanotechnology, Low power circuit design and predictive analytics with CRTC Press and IEEE-Wiley. She has served as reviewer in various International and peer reviewed Journals and conferences and delivered talks at national and international level events. She has also worked as Convener, Session Chair and organizer of various international conferences, summer internships including summer course on Diode Fabrication and Faculty Development Program in the domain of image processing as well as VLSI Testing. She has guided several M Tech Dissertations and B Tech projects and guiding PhD scholars as well. She is a Senior Member of IEEE. Dr Shilpi Birla is working as a Professor in Electronics & Communication Department at Manipal University Jaipur. She has a teaching and industrial experience of more than 15 years. She did her Ph D in Low Power VLSI Design. Her research interests are Low Power VLSI Design, Memory Circuits, Digital VLSI Circuits, Nanodevices and Image Processing. She has authored more than 60 research papers in journals of repute and International conferences. She has organized several workshops in HSPICE, TCAD and XILINX, Summer internships in Diode Fabrication and Faculty Development Programs. She has worked as a session chair, conference steering committee member, editorial board member, and reviewer in international/national IEEE Journal and conferences. She has guided many M. Tech Students and guiding Ph.D. students. She is a senior member of IEEE. Mr. Chetan Arvind Patil is a Principal Engineer at Marvell Semiconductor Inc., USA, with over 10+ years of experience in the semiconductor industry. He focuses on Test Engineering and Customer Strategy for AI custom ASICs, driving scalable test methodologies, yield optimization, and manufacturing readiness for advanced compute silicon. He is actively engaged in global semiconductor initiatives spanning standards, industry forums, and roadmap development. He contributes to various IEEE initiatives, including IEEE Global Semiconductors (an Ad Hoc of the IEEE Future Directions Committee), supporting technical discussions on AI-driven semiconductor development, manufacturing scalability, and ecosystem evolution. He is actively involved in IEEE Standards activities, serves on the IEEE Senior Member Application Panel, and contributes as a committee member and reviewer for multiple IEEE conferences. He has also contributed to the Heterogeneous Integration Roadmap under the IEEE Electronics Packaging Society (EPS) and delivered 15+ invited talks at global universities and industry forums, and has supported the MAPT Roadmap under the Semiconductor Research Corporation. Chetan is the author of 30+ semiconductor-focused articles covering yield, testing, chiplets, reliability, and manufacturing trends, published in international industry media. He also maintains a semiconductor blog, www.ChetanPatil.in, with 300+ articles aimed at knowledge sharing across the ecosystem. He holds dual Master of Science degrees in Computer Engineering from Arizona State University and Northwestern University, and a Bachelor of Engineering in Electronics and Telecommunication from Pune Institute of Computer Technology, India. He is a Senior Member of IEEE.

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• 1. Automation in Analog Circuit Design using AI2. Neural Network for Logic Synthesis Optimization3. Machine Learning Approaches to Fault Detection in Circuit Design4. Enhancing Chip Verification using AI5. AI Applications in Digital Design for Testability (DFT6. Machine leaning based power estimation in VLSI Design7. Next-Gen IC Fault Detection using Advanced Machine Learning Algorithms – A Comprehensive Survey8. AI-driven high level synthesis and behavioral simulation in VLSI design9. Leveraging machine learning algorithms for designing analog and RF integrated circuits10. Challenges with traditional integrated circuits design methods11. Optimization techniques in ML for VLSI design

Dr Neha Singh is a well-rounded and dynamic teaching professional with 20+ years of in-depth experience in educating undergraduate and postgraduate engineering students in Electronics & Communication Engineering. She is currently working as Assistant Professor, in the Department of Electronics & Communication Engineering at Manipal University Jaipur, Rajasthan, India. She did her PhD in the year 2020. Her areas of research interest include Image Processing, Machine learning, VLSI design and nanodevices. She has several papers and book chapters published in Journals, books and conferences of repute. She has co-authored engineering textbooks and edited three Scopus indexed books on Nanotechnology, Low power circuit design and predictive analytics with CRTC Press and IEEE-Wiley. She has served as reviewer in various International and peer reviewed Journals and conferences and delivered talks at national and international level events. She has also worked as Convener, Session Chair and organizer of various international conferences, summer internships including summer course on Diode Fabrication and Faculty Development Program in the domain of image processing as well as VLSI Testing. She has guided several M Tech Dissertations and B Tech projects and guiding PhD scholars as well. She is a Senior Member of IEEE. Dr Shilpi Birla is working as a Professor in Electronics & Communication Department at Manipal University Jaipur. She has a teaching and industrial experience of more than 15 years. She did her Ph D in Low Power VLSI Design. Her research interests are Low Power VLSI Design, Memory Circuits, Digital VLSI Circuits, Nanodevices and Image Processing. She has authored more than 60 research papers in journals of repute and International conferences. She has organized several workshops in HSPICE, TCAD and XILINX, Summer internships in Diode Fabrication and Faculty Development Programs. She has worked as a session chair, conference steering committee member, editorial board member, and reviewer in international/national IEEE Journal and conferences. She has guided many M. Tech Students and guiding Ph.D. students. She is a senior member of IEEE. Mr. Chetan Arvind Patil is a Principal Engineer at Marvell Semiconductor Inc., USA, with over 10+ years of experience in the semiconductor industry. He focuses on Test Engineering and Customer Strategy for AI custom ASICs, driving scalable test methodologies, yield optimization, and manufacturing readiness for advanced compute silicon. He is actively engaged in global semiconductor initiatives spanning standards, industry forums, and roadmap development. He contributes to various IEEE initiatives, including IEEE Global Semiconductors (an Ad Hoc of the IEEE Future Directions Committee), supporting technical discussions on AI-driven semiconductor development, manufacturing scalability, and ecosystem evolution. He is actively involved in IEEE Standards activities, serves on the IEEE Senior Member Application Panel, and contributes as a committee member and reviewer for multiple IEEE conferences. He has also contributed to the Heterogeneous Integration Roadmap under the IEEE Electronics Packaging Society (EPS) and delivered 15+ invited talks at global universities and industry forums, and has supported the MAPT Roadmap under the Semiconductor Research Corporation. Chetan is the author of 30+ semiconductor-focused articles covering yield, testing, chiplets, reliability, and manufacturing trends, published in international industry media. He also maintains a semiconductor blog, www.ChetanPatil.in, with 300+ articles aimed at knowledge sharing across the ecosystem. He holds dual Master of Science degrees in Computer Engineering from Arizona State University and Northwestern University, and a Bachelor of Engineering in Electronics and Telecommunication from Pune Institute of Computer Technology, India. He is a Senior Member of IEEE.

Select Guide Rating

• 1. Automation in Analog Circuit Design using AI2. Neural Network for Logic Synthesis Optimization3. Machine Learning Approaches to Fault Detection in Circuit Design4. Enhancing Chip Verification using AI5. AI Applications in Digital Design for Testability (DFT6. Machine leaning based power estimation in VLSI Design7. Next-Gen IC Fault Detection using Advanced Machine Learning Algorithms – A Comprehensive Survey8. AI-driven high level synthesis and behavioral simulation in VLSI design9. Leveraging machine learning algorithms for designing analog and RF integrated circuits10. Challenges with traditional integrated circuits design methods11. Optimization techniques in ML for VLSI design

Dr Neha Singh is a well-rounded and dynamic teaching professional with 20+ years of in-depth experience in educating undergraduate and postgraduate engineering students in Electronics & Communication Engineering. She is currently working as Assistant Professor, in the Department of Electronics & Communication Engineering at Manipal University Jaipur, Rajasthan, India. She did her PhD in the year 2020. Her areas of research interest include Image Processing, Machine learning, VLSI design and nanodevices. She has several papers and book chapters published in Journals, books and conferences of repute. She has co-authored engineering textbooks and edited three Scopus indexed books on Nanotechnology, Low power circuit design and predictive analytics with CRTC Press and IEEE-Wiley. She has served as reviewer in various International and peer reviewed Journals and conferences and delivered talks at national and international level events. She has also worked as Convener, Session Chair and organizer of various international conferences, summer internships including summer course on Diode Fabrication and Faculty Development Program in the domain of image processing as well as VLSI Testing. She has guided several M Tech Dissertations and B Tech projects and guiding PhD scholars as well. She is a Senior Member of IEEE. Dr Shilpi Birla is working as a Professor in Electronics & Communication Department at Manipal University Jaipur. She has a teaching and industrial experience of more than 15 years. She did her Ph D in Low Power VLSI Design. Her research interests are Low Power VLSI Design, Memory Circuits, Digital VLSI Circuits, Nanodevices and Image Processing. She has authored more than 60 research papers in journals of repute and International conferences. She has organized several workshops in HSPICE, TCAD and XILINX, Summer internships in Diode Fabrication and Faculty Development Programs. She has worked as a session chair, conference steering committee member, editorial board member, and reviewer in international/national IEEE Journal and conferences. She has guided many M. Tech Students and guiding Ph.D. students. She is a senior member of IEEE. Mr. Chetan Arvind Patil is a Principal Engineer at Marvell Semiconductor Inc., USA, with over 10+ years of experience in the semiconductor industry. He focuses on Test Engineering and Customer Strategy for AI custom ASICs, driving scalable test methodologies, yield optimization, and manufacturing readiness for advanced compute silicon. He is actively engaged in global semiconductor initiatives spanning standards, industry forums, and roadmap development. He contributes to various IEEE initiatives, including IEEE Global Semiconductors (an Ad Hoc of the IEEE Future Directions Committee), supporting technical discussions on AI-driven semiconductor development, manufacturing scalability, and ecosystem evolution. He is actively involved in IEEE Standards activities, serves on the IEEE Senior Member Application Panel, and contributes as a committee member and reviewer for multiple IEEE conferences. He has also contributed to the Heterogeneous Integration Roadmap under the IEEE Electronics Packaging Society (EPS) and delivered 15+ invited talks at global universities and industry forums, and has supported the MAPT Roadmap under the Semiconductor Research Corporation. Chetan is the author of 30+ semiconductor-focused articles covering yield, testing, chiplets, reliability, and manufacturing trends, published in international industry media. He also maintains a semiconductor blog, www.ChetanPatil.in, with 300+ articles aimed at knowledge sharing across the ecosystem. He holds dual Master of Science degrees in Computer Engineering from Arizona State University and Northwestern University, and a Bachelor of Engineering in Electronics and Telecommunication from Pune Institute of Computer Technology, India. He is a Senior Member of IEEE.

Select Guide Rating

• 1. Automation in Analog Circuit Design using AI2. Neural Network for Logic Synthesis Optimization3. Machine Learning Approaches to Fault Detection in Circuit Design4. Enhancing Chip Verification using AI5. AI Applications in Digital Design for Testability (DFT6. Machine leaning based power estimation in VLSI Design7. Next-Gen IC Fault Detection using Advanced Machine Learning Algorithms – A Comprehensive Survey8. AI-driven high level synthesis and behavioral simulation in VLSI design9. Leveraging machine learning algorithms for designing analog and RF integrated circuits10. Challenges with traditional integrated circuits design methods11. Optimization techniques in ML for VLSI design