Formal Semantics for VHDL

It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic. If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. This text puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism. Two chapters use Petri nets as target language and two of them higher order logic. Two use functional concepts and finally another uses the concept of evolving algebras. "Formal Semantics for VHDL" is intended for researchers in formal methods and can be used as a text for an advanced course on the subject.