Frank Hannig – författare

This book makes powerful Field Programmable GateArray (FPGA) and reconfigurable technology accessible to software engineers bycovering different state-of-the-art high-level synthesis approaches (e.g.,OpenCL and several C-to-gates compilers). It introduces FPGA technology, itsprogramming model, and how various applications can be implemented on FPGAswithout going through low-level hardware design phases. Readers will get arealistic sense for problems that are suited for FPGAs and how to implementthem from a software designer’s point of view. The authors demonstrate that FPGAs and their programming model reflectthe needs of stream processing problems much better than traditional CPU or GPUarchitectures, making them well-suited for a wide variety of systems, fromembedded systems performing sensor processing to large setups for Big Datanumber crunching.  This book serves as aninvaluable tool for software designers and FPGA design engineers who are interestedin high design productivity through behavioural synthesis, domain-specificcompilation, and FPGA overlays.

This book constitutes theproceedings of the 29th International Conference on Architecture of ComputingSystems, ARCS 2016, held in Nuremberg, Germany, in April 2016.The 29 full papers presented in this volume werecarefully reviewed and selected from 87 submissions. They were organized intopical sections named: configurable and in-memory accelerators;network-on-chip and secure computing architectures; cache architectures andprotocols; mapping of applications on heterogeneous architectures and real-timetasks on multiprocessors; all about time: timing, tracing, and performancemodeling; approximate and energy-efficient computing; allocation: from memoriesto FPGA hardware modules; organic computing systems; and reliability aspects inNoCs, caches, and GPUs.

This book introduces new compilation techniques, using the polyhedron model for the resource-adaptive parallel execution of loop programs on massively parallel processor arrays. The authors show how to compute optimal symbolic assignments and parallel schedules of loop iterations at compile time, for cases where the number of available cores becomes known only at runtime. The compile/runtime symbolic parallelization approach the authors describe reduces significantly the runtime overhead, compared to dynamic or just‐in-time compilation. The new, on‐demand fault‐tolerant loop processing approach described in this book protects loop nests for parallel execution against soft errors.