Harry D. Foster – författare

Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user’s existing verification environment, in other words the testbench infrastructure.The guiding principles promoted in this book when creating an assertion-based IP monitor are: modularity—assertion-based IP should have a clear separation between detection and actionclarity—assertion-based IP should be written initially focusing on capturing intent (versus optimizations) A unique feature of this book is the fully worked out, detailed examples. The concepts presented in the book are drawn from the authors’ experience developing assertion-based IP, as well as general assertion-based techniques. Creating Assertion-Based IP is an important resource for design and verification engineers.From the Foreword:Creating Assertion-Based IP "…reduces to process the creation of one of the most valuable kinds of VIP: assertion-based VIP…This book will serve as a valuable reference for years to come."Andrew Piziali, Sr. Design Verification EngineerCo-Author, ESL Design and Verification: A Prescription for Electronic System Level MethodologyAuthor, Functional Verification Coverage Measurement and Analysis

The first edition of this text offered a common sense method for simplifying and unifying assertion specification by creating a set of pre-defined specification modules that could be instantiated within the designer's RTL. Since the release of the first edition, an entire industry-wide initiative for assertion specification has emerged based on ideas presented in the first edition. This initiative is known as the Open Verification Library Initiative. This standard enables the design engineer to "specify once", then target the same RTL assertion specification over multiple verification processes, such as traditional simulation, semi-formal and formal verification tools. The Open Verification Library Initiative is an empowering technology that should benefit design and verification engineers while providing unity to the EDA community. The second edition of "Principles of Verifiable RTL Design" expands the discussion of assertion specification.

The focus of Assertion-Based Design is three-fold: How to specify assertions; how to create and adopt a methodology that supports assertion-based design (predominately for RTL design); and what to do with the assertions and methodology once you have them. To support these three over-arching goals, the authors showcase multiple forms of assertion specification: Accellera Open Verification Library (OVL), Accellera Property Specification Language (PSL), and Accellera SystemVerilog. The recommendations and claims the authors make in this book are based on their combined actual experiences in applying an assertion-based methodology to real design and verification as well as their work in developing industry assertion standards.

The focus of Assertion-Based Design, Second Edition is three-fold: To support these three over-arching goals, we showcase multiple forms of assertion specifications: Accellera Open Verification Library (OVL), Accellera Property Specification Language (PSL), and Accellera System Verilog. The recommendations and claims we make in this book are based on our combined actual experiences in applying an assertion-based methodology to real design and verification as well as our work in developing industry assertion standards. Differences between the first edition and the second edition include:

Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user’s existing verification environment, in other words the testbench infrastructure.The guiding principles promoted in this book when creating an assertion-based IP monitor are: modularity—assertion-based IP should have a clear separation between detection and actionclarity—assertion-based IP should be written initially focusing on capturing intent (versus optimizations) A unique feature of this book is the fully worked out, detailed examples. The concepts presented in the book are drawn from the authors’ experience developing assertion-based IP, as well as general assertion-based techniques. Creating Assertion-Based IP is an important resource for design and verification engineers.From the Foreword:Creating Assertion-Based IP "…reduces to process the creation of one of the most valuable kinds of VIP: assertion-based VIP…This book will serve as a valuable reference for years to come."Andrew Piziali, Sr. Design Verification EngineerCo-Author, ESL Design and Verification: A Prescription for Electronic System Level MethodologyAuthor, Functional Verification Coverage Measurement and Analysis

The focus of Assertion-Based Design, Second Edition is three-fold: -How to specify assertions, -How to create and adopt a methodology that supports assertion-based design (predominately for RTL design), -What to do with the assertions and methodology once you have them. To support these three over-arching goals, we showcase multiple forms of assertion specifications: Accellera Open Verification Library (OVL), Accellera Property Specification Language (PSL), and Accellera System Verilog. The recommendations and claims we make in this book are based on our combined actual experiences in applying an assertion-based methodology to real design and verification as well as our work in developing industry assertion standards. Differences between the first edition and the second edition include: -Updates to the manuscript based on newer versions of standards, -Corrections to errata identified during reviewer feedback, -New material that presents techniques on how to avoid common ambiguity errors, -New material that discusses high-level requirements modeling for specification.

There is much excitement in the design and verification community about assertion-based design. The question is, who should study assertion-based design? The emphatic answer is, both design and verification engineers. What may be unintuitive to many design engineers is that adding assertions to RTL code will actually reduce design time, while better documenting design intent. Every design engineer should read this book! Design engineers that add assertions to their design will not only reduce the time needed to complete a design, they will also reduce the number of interruptions from verification engineers to answer questions about design intent and to address verification suite mistakes. With design assertions in place, the majority of the interruptions from verification engineers will be related to actual design problems and the error feedback provided will be more useful to help identify design flaws. A design engineer who does not add assertions to the RTL code will spend more time with verification engineers explaining the design functionality and intended interface requirements, knowledge that is needed by the verification engineer to complete the job of testing the design.

Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process. The intended audience for Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.