Jingsheng Jason Cong – författare
Visar alla böcker från författaren Jingsheng Jason Cong. Handla med fri frakt och snabb leverans.
12 produkter
12 produkter
Inbunden, Engelska, 2007
1 631 kr
Skickas inom 10-15 vardagar
Modern Circuit Placement: Best Practices and Results describes advanced techniques in VLSI circuit placement which is one of the most important steps of the VLSI physical design flow. Physical design addresses the back-end layout stage of the chip design process. As technology scales down, the significance of interconnect optimization becomes much more important and physical design, particularly the placement process, is essential to interconnect optimization.This book has four unique characteristics. First, it focuses on the most recent highly scalable placement techniques used for multi-million gate circuit designs, with consideration of many practical aspects of modern circuit placement, such as density and routability control, mixed-size placement support, and area I/O support. Second the book addresses dominant techniques being used in the field. This book includes all the academic placement tools that competed at the International Symposium on Physical Design (ISPD) placement contest in 2005 and 2006. Although these tools are developed by academia, many core techniques in these tools are being used extensively in industry and represent today’s advanced placement techniques. Third, the book provides quantitative comparison among the various techniques on common benchmark circuits derived from real-life industrial designs. The book includes significant amounts of analysis on each technique, such as trade-offs between quality-of-results (QoR) and runtime. Finally, analysis of the optimality of the placement techniques is included. This is done by utilizing placement benchmarks with known optimal solutions, yet with characteristics similar to real industrial designs. Modern Circuit Placement: Best Practices and Results is a valuable tool and a must-read for graduate students, researchers and CAD tool developers in the VLSI physical synthesis and physical design fields.
E-bok
PDF, Engelska, 20071 977 kr
Läs direkt efter köp
Modern Circuit Placement: Best Practices and Results describes advanced techniques in VLSI circuit placement which is one of the most important steps of the VLSI physical design flow. Physical design addresses the back-end layout stage of the chip design process. As technology scales down, the significance of interconnect optimization becomes much more important and physical design, particularly the placement process, is essential to interconnect optimization.
This book has four unique characteristics. First, it focuses on the most recent highly scalable placement techniques used for multi-million gate circuit designs, with consideration of many practical aspects of modern circuit placement, such as density and routability control, mixed-size placement support, and area I/O support. Second the book addresses dominant techniques being used in the field. This book includes all the academic placement tools that competed at the International Symposium on Physical Design (ISPD) placement contest in 2005 and 2006. Although these tools are developed by academia, many core techniques in these tools are being used extensively in industry and represent today’s advanced placement techniques. Third, the book provides quantitative comparison among the various techniques on common benchmark circuits derived from real-life industrial designs. The book includes significant amounts of analysis on each technique, such as trade-offs between quality-of-results (QoR) and runtime. Finally, analysis of the optimality of the placement techniques is included. This is done by utilizing placement benchmarks with known optimal solutions, yet with characteristics similar to real industrial designs.
Modern Circuit Placement: Best Practices and Results is a valuable tool and a must-read for graduate students, researchers and CAD tool developers in the VLSI physical synthesis and physical design fields.
Del 172 - Springer International Series in Engineering and Computer Science
Fault Covering Problems in Reconfigurable VLSI Systems
Inbunden, Engelska, 1992
1 090 kr
Skickas inom 10-15 vardagar
Fault Covering Problems in Reconfigurable VLSI Systems describes the authors' recent research on reconfiguration problems for fault-tolerance in VLSI and WSI Systems. The book examines solutions to a number of reconfiguration problems. Efficient algorithms are given for tractable covering problems and general techniques are given for dealing with a large number of intractable covering problems. The book begins with an investigation of algorithms for the reconfiguration of large redundant memories. Next, a number of more general covering problems are considered and the complexity of these problems is analyzed. Finally, a general and uniform approach is proposed for solving a wide class of covering problems. The results and techniques described here will be useful to researchers and students working in this area. As such, the book serves as an excellent reference and may be used as the text for an advanced course on the topic.
Inbunden, Engelska, 2003
1 631 kr
Skickas inom 10-15 vardagar
In the last few decades, multiscale algorithms have become a dominant trend in large-scale scientific computation. Researchers have successfully applied these methods to a wide range of simulation and optimization problems. This book gives a general overview of multiscale algorithms; applications to general combinatorial optimization problems such as graph partitioning and the traveling salesman problem; and VLSICAD applications, including circuit partitioning, placement, and VLSI routing. Additional chapters discuss optimization in reconfigurable computing, convergence in multilevel optimization, and model problems with PDE constraints. Audience: Written at the graduate level, the book is intended for engineers and mathematical and computational scientists studying large-scale optimization in electronic design automation.
Inbunden, Engelska, 2009
1 631 kr
Skickas inom 10-15 vardagar
We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore’s law. This observation stated that transistor density in integrated circuits doubles every 1. 5–2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore’s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).
E-bok
PDF, Engelska, 20091 977 kr
Läs direkt efter köp
We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore’s law. This observation stated that transistor density in integrated circuits doubles every 1. 5–2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore’s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).
Häftad, Engelska, 2010
1 631 kr
Skickas inom 10-15 vardagar
Modern Circuit Placement: Best Practices and Results describes advanced techniques in VLSI circuit placement which is one of the most important steps of the VLSI physical design flow. Physical design addresses the back-end layout stage of the chip design process. As technology scales down, the significance of interconnect optimization becomes much more important and physical design, particularly the placement process, is essential to interconnect optimization.This book has four unique characteristics. First, it focuses on the most recent highly scalable placement techniques used for multi-million gate circuit designs, with consideration of many practical aspects of modern circuit placement, such as density and routability control, mixed-size placement support, and area I/O support. Second the book addresses dominant techniques being used in the field. This book includes all the academic placement tools that competed at the International Symposium on Physical Design (ISPD) placement contest in 2005 and 2006. Although these tools are developed by academia, many core techniques in these tools are being used extensively in industry and represent today’s advanced placement techniques. Third, the book provides quantitative comparison among the various techniques on common benchmark circuits derived from real-life industrial designs. The book includes significant amounts of analysis on each technique, such as trade-offs between quality-of-results (QoR) and runtime. Finally, analysis of the optimality of the placement techniques is included. This is done by utilizing placement benchmarks with known optimal solutions, yet with characteristics similar to real industrial designs. Modern Circuit Placement: Best Practices and Results is a valuable tool and a must-read for graduate students, researchers and CAD tool developers in the VLSI physical synthesis and physical design fields.
Del 14 - Combinatorial Optimization
Multilevel Optimization in VLSICAD
Häftad, Engelska, 2011
1 631 kr
Skickas inom 10-15 vardagar
In the last few decades, multiscale algorithms have become a dominant trend in large-scale scientific computation. Researchers have successfully applied these methods to a wide range of simulation and optimization problems. This book gives a general overview of multiscale algorithms; applications to general combinatorial optimization problems such as graph partitioning and the traveling salesman problem; and VLSICAD applications, including circuit partitioning, placement, and VLSI routing. Additional chapters discuss optimization in reconfigurable computing, convergence in multilevel optimization, and model problems with PDE constraints. Audience: Written at the graduate level, the book is intended for engineers and mathematical and computational scientists studying large-scale optimization in electronic design automation.
Del 172 - Springer International Series in Engineering and Computer Science
Fault Covering Problems in Reconfigurable VLSI Systems
Häftad, Engelska, 2012
1 090 kr
Skickas inom 10-15 vardagar
Fault Covering Problems in Reconfigurable VLSI Systems describes the authors' recent research on reconfiguration problems for fault-tolerance in VLSI and WSI Systems. The book examines solutions to a number of reconfiguration problems. Efficient algorithms are given for tractable covering problems and general techniques are given for dealing with a large number of intractable covering problems. The book begins with an investigation of algorithms for the reconfiguration of large redundant memories. Next, a number of more general covering problems are considered and the complexity of these problems is analyzed. Finally, a general and uniform approach is proposed for solving a wide class of covering problems. The results and techniques described here will be useful to researchers and students working in this area. As such, the book serves as an excellent reference and may be used as the text for an advanced course on the topic.
Häftad, Engelska, 2012
1 541 kr
Skickas inom 5-8 vardagar
We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore’s law. This observation stated that transistor density in integrated circuits doubles every 1. 5–2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore’s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).
E-bok
PDF, Engelska, 20121 367 kr
Läs direkt efter köp
Fault Covering Problems in Reconfigurable VLSI Systems describes the authors'' recent research on reconfiguration problems for fault-tolerance in VLSI and WSI Systems. The book examines solutions to a number of reconfiguration problems. Efficient algorithms are given for tractable covering problems and general techniques are given for dealing with a large number of intractable covering problems. The book begins with an investigation of algorithms for the reconfiguration of large redundant memories. Next, a number of more general covering problems are considered and the complexity of these problems is analyzed. Finally, a general and uniform approach is proposed for solving a wide class of covering problems. The results and techniques described here will be useful to researchers and students working in this area. As such, the book serves as an excellent reference and may be used as the text for an advanced course on the topic.
E-bok
PDF, Engelska, 20131 977 kr
Läs direkt efter köp
In the last few decades, multiscale algorithms have become a dominant trend in large-scale scientific computation. Researchers have successfully applied these methods to a wide range of simulation and optimization problems. This book gives a general overview of multiscale algorithms; applications to general combinatorial optimization problems such as graph partitioning and the traveling salesman problem; and VLSICAD applications, including circuit partitioning, placement, and VLSI routing. Additional chapters discuss optimization in reconfigurable computing, convergence in multilevel optimization, and model problems with PDE constraints.
Audience: Written at the graduate level, the book is intended for engineers and mathematical and computational scientists studying large-scale optimization in electronic design automation.