S. Sapatnekar – författare
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9 produkter
Timing Analysis and Optimization of Sequential Circuits
Av Naresh Maheshwari, S. Sapatnekar
Inbunden, 1998
1094 kr
Lägg i varukorg
Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure …
Design Automation for Timing-Driven Layout Synthesis
Av S. Sapatnekar, Sung-Mo (Steve) Kang
Inbunden, 1992
1637 kr
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The automation of layout synthesis design under stringent timing specifications is essential for state-of-the-art VLSI circuits and systems design. Especially, the timing-driven layout synthesis with optimal placement and routing of transistors with proper sizing is most critical in view of the …
Layout Optimization in VLSI Design
Av Bing Lu, Ding-Zhu Du m. fl.
Inbunden, 2001
1639 kr
Lägg i varukorg
The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as interconnect delay, noise, crosstalk, signal integrity, parasitics effects and power dissipation, that invalidate the assumptions that form the basis of …
Layout Optimization in VLSI Design
Av Bing Lu, Ding-Zhu Du m. fl.
Häftad, 2010
1639 kr
Lägg i varukorg
Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form …
Design Automation for Timing-Driven Layout Synthesis
Av S. Sapatnekar, Sung-Mo (Steve) Kang
Häftad, 2012
1639 kr
Lägg i varukorg
Moore's law [Noy77], which predicted that the number of devices in tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be gun to slow down somewhat due to the physical limits of integration technology. Advances in …
Timing Analysis and Optimization of Sequential Circuits
Av Naresh Maheshwari, S. Sapatnekar
Häftad, 2012
1095 kr
Lägg i varukorg
Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure …
Design Automation for Timing-Driven Layout Synthesis
Av Sung-Mo (Steve) Kang, S. Sapatnekar
E-bok, 2012
2111 kr
Lägg i varukorg
Moore''s law [Noy77], which predicted that the number of devices in tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be gun to slow down somewhat due to the physical limits of integration technology. Advances in …
Timing Analysis and Optimization of Sequential Circuits
Av S. Sapatnekar, Naresh Maheshwari
E-bok, 2012
1459 kr
Lägg i varukorg
Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure …
Layout Optimization in VLSI Design
Av S. Sapatnekar, Ding-Zhu Du m. fl.
E-bok, 2013
2111 kr
Lägg i varukorg
Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form …
