Sung-Mo (Steve) Kang - Böcker

This text addresses electrothermal problems in modern VLSI systems. Part I, The Building Blocks, discusses electrothermal phenomena and the fundamental building blocks that electrothermal simulation requires (including power analysis, temperature-dependent device modeling, thermal/electrothermal simulation, and experimental setup-calibration). Part II, The Applications, discusses three important applications of VLSI electrothermal analysis including temperature-dependent electromigration diagnosis, cell-level thermal placement and temperature-driven power and timing analysis. This work should be useful for researchers in the fields of IC reliability analysis and physical design, as well as VLSI designers and graduate students.

The automation of layout synthesis design under stringent timing specifications is essential for state-of-the-art VLSI circuits and systems design. Especially, the timing-driven layout synthesis with optimal placement and routing of transistors with proper sizing is most critical in view of the chip area, interconnection parasitics, circuit delay and power dissipation. This book presents a systematic and unified view of the layout synthesis problem with a strong focus on CMOS technology. The criticality of RC parasitics in the interconnects and the optimal sizing of both p-channel and n-channel transistors are illustrated for motivation. Following the motivation, the problems of modelling circuit delays and transistor sizing are formulated and solved with mathematical rigour. Various delay models for CMOS circuits are discussed to account for realistic interconnection parasitics, the effect of transistor sizes, and also the input slew rates. Also many of the efficient transistor sizing algorithms are critically reviewed and the most recent transistor sizing algorithm based on convex programming techniques is introduced.For design automation of the rigorous CMOS layout synthesis, an integrated system that employs a suite of functional modules is introduced for step-by-step illustration of the design optimization process that produces highly compact CMOS layout that meet used-specified timing and logical nettist requirements. Through most rigorous discussion of the essential design automation process steps and important models and algorithms this book presents a unified systems approach that can be practised for high-performance CMOS VLSI designs. The book should serve as a valuable reference and can be used as text in advanced courses covering VLSI design, especially for design automation of physical design.

This volume addresses the issues related to hot-carrier reliability of MOS VLSI circuits, ranging from device physics to circuit design guidelines. It presents a unified view of the physical mechanisms involved in hot-carrier induced device degradation, the prevalent models for these mechanisms, and simulation methods for estimating hot-carrier effects in the circuit environment. The newly emerging approaches to the VLSI design-for-reliability and rule-based reliability diagnosis are also discussed in detail. Hot-Carrier Reliability of MOS VLSI Circuits is primarily for use by engineers and scientists who study device and circuit-level reliability in VLSI systems and develop practical reliability measures and models. VLSI designers will benefit from this book since it offers a comprehensive overview of the interacting mechanisms that influence hot-carrier reliability, and also provides useful guidelines for reliable VLSI design. This volume can be used as an advanced textbook or reference for a graduate-level course on VLSI reliability.

"Physical Design for Multichip Modules" collects together a large body of research work that has been conducted in recent years in the area of Multichip Module (MCM) design. The material consists of a survey of published results as well as original work by the authors. All major aspects of MCM physical design are discussed, including interconnect analysis and modelling, system partitioning and placement, and multilayer routing. For readers unfamiliar with MCMs, this book presents an overview of the different MCM technologies available today. An in-depth discussion of various recent approaches to interconnect analysis are also presented. Remaining chapters discuss the problems of partitioning, placement, and multilayer routing, with an emphasis on timing performance. Data from a wide range of sources is integrated to present a clear picture of a new, challenging and important research area. The text is suitable for students and researchers looking for interesting research topics. Open problems and suggestions for further research are clearly stated.Points of interest include: an overview of MCM technology and its relationship to physical design; emphasis on performance-driven design, with a chapter devoted to recent techniques for rapid performance analysis and modelling of MCM interconnects; different approaches to multilayer MCM routing collected together and compared; explanation of algorithms is not overly mathematical, yet is detailed enough to give readers a clear understanding of the approach; quantitative data provided wherever possible for comparison of different approaches; and a comprehensive list of references to recent literature on MCMs provided.

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. This text presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behaviour up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue.Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behaviour up to the onset of thermal failure. This text should be suitable for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators should also benefit from the material covered. This book should also be of interest to researchers and first- and second-year graduate students working in semiconductor devices and IC reliability fields.

Physical Design for Multichip Modules collects together a large body of important research work that has been conducted in recent years in the area of Multichip Module (MCM) design. The material consists of a survey of published results as well as original work by the authors. All major aspects of MCM physical design are discussed, including interconnect analysis and modeling, system partitioning and placement, and multilayer routing. For readers unfamiliar with MCMs, this book presents an overview of the different MCM technologies available today. An in-depth discussion of various recent approaches to interconnect analysis are also presented. Remaining chapters discuss the problems of partitioning, placement, and multilayer routing, with an emphasis on timing performance. For the first time, data from a wide range of sources is integrated to present a clear picture of a new, challenging and very important research area. For students and researchers looking for interesting research topics, open problems and suggestions for further research are clearly stated. Points of interest include :Clear overview of MCM technology and its relationship to physical design; Emphasis on performance-driven design, with a chapter devoted to recent techniques for rapid performance analysis and modeling of MCM interconnects; Different approaches to multilayer MCM routing collected together and compared for the first time; Explanation of algorithms is not overly mathematical, yet is detailed enough to give readers a clear understanding of the approach; Quantitative data provided wherever possible for comparison of different approaches; A comprehensive list of references to recent literature on MCMs provided.

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure. Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields.

Moore's law [Noy77], which predicted that the number of devices in­ tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be­ gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design­ ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of chip designers would have to increase at the same rate as the level of integration. Without such an increase in productivity, the design of complex systems might not be achievable within a reasonable time-frame. The rapidly increasing complexity of VLSI circuits has made de- 1 2 INTRODUCTION sign automation an absolute necessity, since the required increase in productivity can only be accomplished with the use of sophisticated design tools. Such tools also enable designers to perform trade-off analyses of different logic implementations and to make well-informed design decisions.

As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada­ tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down­ ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.