Fan-Out Wafer-Level Packaging

SPECIALIZED PROFESSIONAL COMPETENCEDesign, analysis, materials, process, manufacturing, qualification, reliability, testing, and thermal management of electronic and optoelectronic components and systems. SMT, fan-out/fan-in WLP, TSV, 3D IC Integration, heterogeneous integration and SiP. Leadfree soldering, manufacturing, and solder joint reliability. Management of a R&D Laboratory and Company.BACKGROUND AND PROFESSIONAL EXPERIENCEPh.D.  (Theoretical and Applied Mechanics), University of Illinois, Urbana, IL (1977)M.S.   (Engineering Physics), University of Wisconsin, Madison, WI (1974)M.S.   (Structural Mechanics), University of British Columbia, Vancouver, BC (1973)M.S.   (Management Science), Fairleigh Dickinson University, Teaneck, NJ (1981)B.S.   (Civil Engineering), National Taiwan University, Taipei, Taiwan (1970)  ASM PacificTechnology (Sr. Technical Advisor), Hong Kong, July 2014 - PresentIndustrial Technology Research Institute (ITRI Fellow), Taiwan, Jan 2010 – June 2014Hong Kong University of Science & Technology (Visiting Professor), Jan 2009 – Jan 2010Institute of Microelectronic, (Director, System Packaging Lab), Singapore, 2006 - Jan 2009Agilent Technologies, Inc. (Sr. Interconnection Specialist), Santa Clara, CA, 2000-2006 Express Packaging Systems, Inc., (President), Palo Alto, CA, 1995-2000Hewlett-Packard Labs/Company (Senior MTS/Individual Contributor), Palo Alto, CA, 1984-1995Sandia National Laboratories (Member of Technical Staff), Albuquerque, NM, 1982-1983Bechtel Power Corporation (Lead Engineer), San Francisco, CA, 1981-1982Ebasco (Lead Engineer), New York, NY, 1978-1980Exxon Production and Research Company (Research Engineer), Houston, TX, 1977-1978  Editorial Board of ASME Transactions, Journal of Electronic Packaging, 1989-1999Editorial Board of IEEE Transactions on Components, Packaging, Manufacture Technology, 1990-1995Editor-in-Chief, Circuit World, 1998-2000.Program Chair ('90) to General Chair ('92) of the IEEE/CPMT IEMTSProgram Chair ('93) to General Chair ('95) of the IEEE/CPMT ECTC Publication Chair for IEEE/ECTC Symposium Organizer/Chair of the ASME Winter Annual Meeting, 1987-2002ASME Distinguish Lecturer (2000-2003), IEEE/CPMT Distinguish Lecturer (1998-present)  ASME Worcester Reed Warner Medal (2015)IEEE Components Packaging and Manufacturing Technology Field Award (2013)IMAPS William Ashman Achievement Award (2013)Pan Wen Yuan Distinguished Research Award (2011) IEEE/CPMT Outstanding Sustained Technical Contribution Award (2010)Best IEEE Transactions Paper Award (2010 Components Packaging and Manufacturing Technology)Outstanding Paper Award (2009 IEEE EPTC) SME Total Excellence in Electronics Manufacturing Award (2001) Best ASME Transactions Paper Award (2000 Journal of Electronic Packaging)IEEE/CPMT Outstanding Contribution Awards (2000)IEEE Meritorious Achievement Award in Continuing Education (2000)   ASME/EEP Technical Achievement Award (1998)IEEE/CPMT Manufacturing Awards (1994)Best of Conference Paper Award (1989 IEEE ECTC)IEEE Fellow (since 1994), ASME Fellow (since 1999), IMAPS Fellow (since 2013)Over 20 books, 450 peer-reviewed papers, 30 issued and pending patents, and 290 keynotes/lectures.

“It is a good resource to demonstrate the many facets of advance packaging engineering and can serve as a very informative technical reference. Valuable as a learning tool of semiconductor packaging and reliability, its clear relevance to real world industry practices make it useful for both academics and semiconductor industry practitioners.” (Chong Leong Gan and Hem Takiar, Life Cycle Reliability and Safety Engineering, June 8, 2020)“This is a unique book written by well known & distinguished expert Dr. John Lau … reading this book will be an eye-opening journal to all who want to truly understand fan-out wafer level packaging. You will find so many details and state-of-the-art information in this book. … I consider this is an excellent book with great value either to read or as a reference resource, and definitely I will strongly recommend it to my colleagues and friends.” (Yong Liu, Amazon.com, June, 2018)

• Patent Issues of Fan-out Wafer-Level Packaging.- Flip Chip Technology vs. FOWLP.- Fan-In Wafer-Level Packaging vs. FOWLP.- Embedded Chip Packaging.- FOWLP: Chip-First and Die Face-Down.- FOWLP: Chip-First and Die Face-Up.- FOWLP: Chip-Last or RDL-First.- FOWLP: PoP with FOWLP.- Fan-Out Panel-Level Packaging (FOPLP).- 3D Integration.- Heterogeneous Integration.