Niraj K. Jha – författare

Understand the structure, behaviour, and limitations of logic machines with this thoroughly updated third edition. Many new topics are included, such as CMOS gates, logic synthesis, logic design for emerging nanotechnologies, digital system testing, and asynchronous circuit design, to bring students up-to-speed with modern developments. The intuitive examples and minimal formalism of the previous edition are retained, giving students a text that is logical and easy to follow, yet rigorous. Kohavi and Jha begin with the basics, and then cover combinational logic design and testing, before moving on to more advanced topics in finite-state machine design and testing. Theory is made easier to understand with 200 illustrative examples, and students can test their understanding with over 350 end-of-chapter review questions.

This volume presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behaviour) levels of the design hierarchy, which are often the levels that yield the most power savings. It describes power estimation and optimization techniques for use during high-level (behavioural synthesis), as well as for designs expressed at the register-transfer or architecture level. The book surveys research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power. It should be of use to students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.

In the last few years CMOS technology has become increas­ ingly dominant for realizing Very Large Scale Integrated (VLSI) circuits. The popularity of this technology is due to its high den­ sity and low power requirement. The ability to realize very com­ plex circuits on a single chip has brought about a revolution in the world of electronics and computers. However, the rapid advance­ ments in this area pose many new problems in the area of testing. Testing has become a very time-consuming process. In order to ease the burden of testing, many schemes for designing the circuit for improved testability have been presented. These design for testability techniques have begun to catch the attention of chip manufacturers. The trend is towards placing increased emphasis on these techniques. Another byproduct of the increase in the complexity of chips is their higher susceptibility to faults. In order to take care of this problem, we need to build fault-tolerant systems. The area of fault-tolerant computing has steadily gained in importance. Today many universities offer courses in the areas of digital system testing and fault-tolerant computing. Due to the impor­ tance of CMOS technology, a significant portion of these courses may be devoted to CMOS testing. This book has been written as a reference text for such courses offered at the senior or graduate level. Familiarity with logic design and switching theory is assumed. The book should also prove to be useful to professionals working in the semiconductor industry.

This book is about large-scale electronic circuits design driven by nanotechnology, where nanotechnology is broadly defined as building circuits using nanoscale devices that are either implemented with nanomaterials (e.g., nanotubes or nanowires) or following an unconventional method (e.g., FinFET or III/V compound-based devices). These nanoscale devices have significant potential to revolutionize the fabrication and integration of electronic systems and scale beyond the perceived scaling limitations of traditional CMOS.While innovations in nanotechnology originate at the individual device level, realizing the true impact of electronic systems demands that these device-level capabilities be translated into system-level benefits. This is the first book to focus on nanoscale circuits and their design issues, bridging the existing gap between nanodevice research and nanosystem design.

In the last few years CMOS technology has become increas­ ingly dominant for realizing Very Large Scale Integrated (VLSI) circuits. The popularity of this technology is due to its high den­ sity and low power requirement. The ability to realize very com­ plex circuits on a single chip has brought about a revolution in the world of electronics and computers. However, the rapid advance­ ments in this area pose many new problems in the area of testing. Testing has become a very time-consuming process. In order to ease the burden of testing, many schemes for designing the circuit for improved testability have been presented. These design for testability techniques have begun to catch the attention of chip manufacturers. The trend is towards placing increased emphasis on these techniques. Another byproduct of the increase in the complexity of chips is their higher susceptibility to faults. In order to take care of this problem, we need to build fault-tolerant systems. The area of fault-tolerant computing has steadily gained in importance. Today many universities offer courses in the areas of digital system testing and fault-tolerant computing. Due to the impor­ tance of CMOS technology, a significant portion of these courses may be devoted to CMOS testing. This book has been written as a reference text for such courses offered at the senior or graduate level. Familiarity with logic design and switching theory is assumed. The book should also prove to be useful to professionals working in the semiconductor industry.

High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level. High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power. High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.

This book is about large-scale electronic circuits design driven by nanotechnology, where nanotechnology is broadly defined as building circuits using nanoscale devices that are either implemented with nanomaterials (e.g., nanotubes or nanowires) or following an unconventional method (e.g., FinFET or III/V compound-based devices). These nanoscale devices have significant potential to revolutionize the fabrication and integration of electronic systems and scale beyond the perceived scaling limitations of traditional CMOS.While innovations in nanotechnology originate at the individual device level, realizing the true impact of electronic systems demands that these device-level capabilities be translated into system-level benefits. This is the first book to focus on nanoscale circuits and their design issues, bridging the existing gap between nanodevice research and nanosystem design.