ESD Testing

Dr Steven H. Voldman, IEEE Fellow, Vermont, USADr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for "Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology." Voldman was a member of the semiconductor development of IBM for 25 years as well as a consultant for TSMC, and Samsung Electronics. Dr. Voldman initiated the first transmission line pulse (TLP) standard development team, and a participant in the JEDEC-ESD Association standards harmonization of the human body model (HBM) Standard. From 2000 to 2013, as Chairman of the ESD Association Work Group on TLP and very-fast TLP (VF-TLP), his team was responsible for initiating the first standard practice and standards for TLP and VF-TLP. He initiated the "ESD on Campus" program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 40 universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, and China. Dr. Voldman teaches short courses and tutorials on ESD, latchup, patenting, and invention.

• About the Author xviiPreface xixAcknowledgments xxiii1 Introduction 11.1 Testing for ESD, EMI, EOS, EMC, and Latchup 11.2 Component and System Level Testing 11.3 Qualification Testing 21.4 ESD Standards 31.4.1 Standard Development – Standard Practice (SP) and Standard Test Methods (STMs) 31.4.2 Repeatability 41.4.3 Reproducibility 41.4.4 Round Robin Testing 41.4.5 Round Robin Statistical Analysis – k-Statistics 51.4.6 Round Robin Statistical Analysis – h-Statistics 61.5 Component Level Standards 61.6 System Level Standards 71.7 Factory and Material Standards 71.8 Characterization Testing 81.8.1 Semiconductor Component Level Characterization 91.8.2 Semiconductor Device Level Characterization 91.8.3 Wafer Level ESD Characterization Testing 91.8.4 Device Characterization Tests on Circuits 101.8.5 Device Characterization Tests on Components 101.8.6 System level Characterization on Components 111.8.7 Testing to Standard Specification Levels 111.8.8 Testing to Failure 111.9 ESD Library Characterization and Qualification 121.10 ESD Component Standards and Chip Architectures 121.10.1 Relationship Between ESD Standard Pin Combinations and Failure Mechanisms 121.10.2 Relationship Between ESD Standard Pin Combinations and Chip Architecture 131.11 System Level Characterization 131.12 Summary and Closing Comments 13Problems 14References 152 Human Body Model 172.1 History 172.2 Scope 182.3 Purpose 182.4 Pulse Waveform 182.5 Equivalent Circuit 192.6 Test Equipment 202.7 Test Sequence and Procedure 232.8 Failure Mechanisms 252.9 HBM ESD Current Paths 262.10 HBM ESD Protection Circuit Solutions 282.11 Alternate Test Methods 322.11.1 HBM Split Fixture Testing 322.11.2 HBM Sample Testing 332.11.3 HBM Wafer Level ESD Testing 332.11.4 HBM Test Extraction Across the Device Under Test (DUT) 332.12 HBM Two-Pin Stress 342.12.1 HBM Two-Pin Stress – Advantages 372.12.2 HBM Two-Pin Stress – Pin Combinations 372.13 HBM Small Step Stress 372.13.1 HBM Small Step Stress – Advantages 382.13.2 HBM Small Step Stress – Data Analysis Methods 382.13.3 HBM Small Step Stress – Design Optimization 382.14 Summary and Closing Comments 38Problems 39References 393 Machine Model 433.1 History 433.2 Scope 433.3 Purpose 433.4 Pulse Waveform 443.4.1 Comparison of Machine Model (MM) and Human Body Model (HBM) Pulse Waveform 443.5 Equivalent Circuit 453.6 Test Equipment 453.7 Test Sequence and Procedure 473.8 Failure Mechanisms 493.9 mm ESD Current Paths 493.10 mm ESD Protection Circuit Solutions 523.11 Alternate Test Methods 553.11.1 Small Charge Model (SCM) 553.12 Machine Model to Human Body Model Ratio 573.13 Machine Model Status as an ESD Standard 583.14 Summary and Closing Comments 58Problems 59References 594 Charged Device Model (CDM) 614.1 History 614.2 Scope 614.3 Purpose 624.4 Pulse Waveform 624.4.1 Charged Device Model Pulse Waveform 624.4.2 Comparison of Charged Device Model (CDM) and Human Body Model (HBM) Pulse Waveform 634.5 Equivalent Circuit 654.6 Test Equipment 654.7 Test Sequence and Procedure 674.8 Failure Mechanisms 694.9 CDM ESD Current Paths 704.10 CDM ESD Protection Circuit Solutions 724.11 Alternative Test Methods 744.11.1 Alternative Test Methods – Socketed Device Model (SDM) 744.12 Charged Board Model (CBM) 754.12.1 Comparison of Charged Board Model (CBM) and Charged Device Model (CDM) Pulse Waveform 754.12.2 Charged Board Model (CBM) as an ESD Standard 774.13 Summary and Closing Comments 77Problems 79References 805 Transmission Line Pulse (TLP) Testing 845.1 History 845.2 Scope 855.3 Purpose 855.4 Pulse Waveform 865.5 Equivalent Circuit 875.6 Test Equipment 885.6.1 Current Source 905.6.2 Time Domain Reflection (TDR) 905.6.3 Time Domain Transmission (TDT) 915.6.4 Time Domain Reflection and Transmission (TDRT) 915.6.5 Commercial Transmission Line Pulse (TLP) Systems 925.7 Test Sequence and Procedure 955.7.1 TLP Pulse Analysis 965.7.2 Measurement Window 965.7.3 Measurement Analysis – TDR Voltage Waveform 965.7.4 Measurement Analysis – Time Domain Reflection (TDR) Current Waveform 975.7.5 Measurement Analysis – Time Domain Reflection (TDR) Current–Voltage Characteristic 985.8 TLP Pulsed I–V Characteristic 985.8.1 TLP I–V Characteristic Key Parameters 995.8.2 TLP Power Versus Time 995.8.3 TLP Power Versus Time – Measurement Analysis 1005.8.4 TLP Power-to-Failure Versus Pulse Width Plot 1005.9 Alternate Methods 1015.9.1 Long Duration TLP (LD-TLP) 1015.9.2 Long Duration TLP Time Domain 1025.10 TLP-to-HBM Ratio 1045.10.1 Comparison of Transmission Line Pulse (TLP) and Human Body Model (HBM) Pulse Width 1045.11 Summary and Closing Comments 104Problems 104References 1056 Very Fast Transmission Line Pulse (VF-TLP) Testing 1086.1 History 1086.2 Scope 1086.3 Purpose 1086.4 Pulse Waveform 1096.4.1 Comparison of VF-TLP Versus TLP Waveform 1106.5 Equivalent Circuit 1116.6 Test Equipment Configuration 1116.6.1 Current Source 1126.6.2 Time Domain Reflection (TDR) 1126.6.3 Time Domain Transmission (TDT) 1126.6.4 Time Domain Reflection and Transmission (TDRT) 1136.6.5 Early VF-TLP Systems 1146.6.6 Commercial VF-TLP Test Systems 1166.7 Test Sequence and Procedure 1176.7.1 VF-TLP Pulse Analysis 1186.7.2 Measurement Window 1186.7.3 Measurement Analysis – VF-TLP Voltage Waveform 1186.7.4 Measurement Analysis – Time Domain Reflectometry (TDR) Current Waveform 1186.7.5 Measurement Analysis – Time Domain Transmission (TDR) Current–Voltage Characteristics 1196.8 VF-TLP Pulsed I–V Characteristics 1216.8.1 VF-TLP Pulsed I–V Characteristic Key Parameters 1216.8.2 VF-TLP Power Versus Time Plot 1226.8.3 VF-TLP Power Versus Time – Measurement Analysis 1236.8.4 VF-TLP Power-to-Failure Versus Pulse Width Plot 1236.8.5 VF-TLP and TLP Power-to-Failure Plot 1246.9 Alternate Test Methods 1246.9.1 Radio Frequency (RF) VF-TLP Systems 1246.9.2 Ultrafast Transmission Line Pulse (UF-TLP) 1256.10 Summary and Closing Comments 125Problems 128References 1287 Iec 61000-4-2 1307.1 History 1307.2 Scope 1307.3 Purpose 1307.3.1 Air Discharge 1317.3.2 Direct Contact Discharge 1317.4 Pulse Waveform 1317.4.1 Pulse Waveform Equation 1327.5 Equivalent Circuit 1337.6 Test Equipment 1337.6.1 Test Configuration 1347.6.2 ESD Guns 1347.6.3 ESD Guns – Standard Versus Discharge Module 1357.6.4 Human Body Model Versus IEC 61000-4-2 1357.7 Test Sequence and Procedure 1357.8 Failure Mechanisms 1377.9 IEC 61000-4-2 ESD Current Paths 1387.10 ESD Protection Circuitry Solutions 1397.11 Alternative Test Methods 1407.11.1 Automotive ESD Standards 1417.11.2 Medical ESD Standards 1427.11.3 Avionic ESD Standard 1437.11.4 Military-Related ESD Standard 1437.12 Summary and Closing Comments 143Problems 143References 1448 Human Metal Model (HMM) 1478.1 History 1478.2 Scope 1478.3 Purpose 1488.4 Pulse Waveform 1488.4.1 Pulse Waveform Equation 1488.5 Equivalent Circuit 1498.6 Test Equipment 1498.7 Test Configuration 1508.7.1 Horizontal Configuration 1518.7.2 Vertical Configuration 1518.7.3 HMM Fixture Board 1528.8 Test Sequence and Procedure 1538.8.1 Current Waveform Verification 1548.8.2 Current Probe Verification Methodology 1548.8.3 Current Probe Waveform Comparison 1568.9 Failure Mechanisms 1578.10 ESD Current Paths 1588.11 ESD Protection Circuit Solutions 1588.12 Summary and Closing Comments 160Problems 160References 1619 Iec 61000-4-5 1639.1 History 1639.2 Scope 1649.3 Purpose 1649.4 Pulse Waveform 1659.5 Equivalent Circuit 1669.6 Test Equipment 1669.7 Test Sequence and Procedure 1689.8 Failure Mechanisms 1689.9 IEC 61000-4-5 ESD Current Paths 1709.10 ESD Protection Circuit Solutions 1709.11 Alternate Test Methods 1719.12 Summary and Closing Comments 171Problems 172References 17210 Cable Discharge Event (CDE) 17410.1 History 17410.2 Scope 17510.3 Purpose 17510.4 Cable Discharge Event – Charging, Discharging, and Pulse Waveform 17510.4.1 Charging Process 17610.4.2 Discharging Process 17610.4.3 Pulse Waveform 17610.4.4 Comparison of CDE and IEC 61000-4-2 Pulse Waveform 17610.5 Equivalent Circuit 17810.6 Test Equipment 17910.6.1 Commercial Test Systems 17910.7 Test Measurement 18010.7.1 Measurement 18010.7.2 Measurement –Transmission Line Test Generators 18010.7.3 Measurement – Low-Impedance Transmission Line Waveform 18110.7.4 Schematic Capturing System Response to Reference Waveform 18210.7.5 Tapered Transmission Lines 18510.7.6 ESD Current Sensor 18510.8 Test Procedure 18510.9 Measurement of a Cable in Different Conditions 18510.9.1 Test System Configuration and Diagram 18710.9.2 Cable Configurations – Handheld Cable 18910.9.3 Cable Configuration – Taped to Ground Plane 19110.9.4 Cable Configurations – Pulse Analysis Summary 19110.10 Transient Field Measurements 19510.10.1 Transient Field Measurement of Short-Length Cable Discharge Events 19510.10.2 Antenna-Induced Voltages 19510.11 Telecommunication Cable Discharge Test System 19510.12 Cable Discharge Current Paths 20010.13 Failure Mechanisms 20010.13.1 Cable Discharge Event Failure – Connector Failure 20010.13.2 Cable Discharge Event Failure – Printed Circuit Board 20110.13.3 Cable Discharge Event Failure – Semiconductor On-Chip 20110.13.4 Cable Discharge Event (CDE)-Induced Latchup 20110.14 Cable Discharge Event (CDE) Protection 20110.14.1 RJ-45 Connectors 20210.14.2 Printed Circuit Board Design Considerations 20210.14.3 ESD Circuitry 20210.14.4 Cable Discharge Event (CDE) ESD Protection Validation 20310.15 Alternative Test Methods 20310.16 Summary and Closing Comments 204Problems 204References 20411 Latchup 20611.1 History 20611.2 Purpose 20811.3 Scope 20911.4 Pulse Waveform 20911.5 Equivalent Circuit 20911.6 Test Equipment 20911.7 Test Sequence and Procedure 21111.8 Failure Mechanisms 21511.9 Latchup Current Paths 21611.10 Latchup Protection Solutions 21611.10.1 Latchup Protection Solutions – Semiconductor Process 21911.10.2 Latchup Protection Solutions – Design Layout 21911.10.3 Latchup Protection Solutions – Circuit Design 22011.10.4 Latchup Protection Solutions – System Level Design 22111.11 Alternate Test Methods 22211.11.1 Photoemission Techniques – PICA–TLP 22211.11.2 Photoemission Techniques – CCD Method 22411.12 Single Event Latchup (SEL) Test Methods 22411.13 Summary and Closing Comments 224Problems 227References 22712 Electrical Overstress (EOS) 23012.1 History 23012.2 Scope 23212.3 Purpose 23312.4 Pulse Waveform 23312.5 Equivalent Circuit 23312.6 Test Equipment 23412.7 Test Procedure and Sequence 23412.8 Failure Mechanisms 23612.8.1 Information Gathering 23612.8.2 Failure Verification 23712.8.3 Failure Site Identification and Localization 23712.8.4 Root Cause Determination 23812.8.5 Feedback of Root Cause 23812.8.6 Corrective Actions 23812.8.7 Documentation Reports 23812.8.8 Statistical Analysis, Record Retention, and Control 23812.9 Electrical Overstress (EOS) Protection Circuit Solutions 24012.10 Electrical Overstress (EOS) Testing – TLP Method and EOS 24912.10.1 Electrical Overstress (EOS) Testing – Long Duration Transmission Line Pulse (LD-TLP) Method 25012.10.2 Electrical Overstress (EOS) Testing – Transmission Line Pulse (TLP) Method, EOS, and the Wunsch–Bell Model 25012.10.3 Electrical Overstress (EOS) Testing – Limitations of the Transmission Line Pulse (TLP) Method for the Evaluation of EOS for Systems 25012.10.4 Electrical Overstress (EOS) Testing – Electromagnetic Pulse (EMP) 25112.11 Electrical Overstress (EOS) Testing – DC and Transient Latchup Testing 25212.12 Summary and Closing Comments 252Problems 252References 25313 Electromagnetic Compatibility (EMC) 25713.1 History 25713.2 Purpose 25813.3 Scope 25813.4 Pulse Waveform 25813.5 Equivalent Circuit 25913.6 Test Equipment 25913.6.1 Commercial Test System 25913.6.2 Scanning Systems 26013.7 Test Procedures 26113.7.1 ESD/EMC Scanning Test Procedure and Method 26113.8 Failure Mechanisms 26113.9 ESD/EMC Current Paths 26313.10 EMC Solutions 26413.11 Alternative Test Methods 26613.11.1 Scanning Methodologies 26613.11.2 Testing – Susceptibility and Vulnerability 26613.11.3 EMC/ESD Scanning – Semiconductor Component and Populated Printed Circuit Board 26713.12 EMC/ESD Product Evaluation – IC Prequalification 26713.13 EMC/ESD Scanning Detection – Upset Evaluation 26713.13.1 ESD/EMC Scanning Stimulus 26713.14 EMC/ESD Product Qualification Process 26813.14.1 EMC/ESD Reproducibility 26813.14.2 EMC/ESD Failure Threshold Mapping and Histogram 26813.14.3 ESD Immunity Test – IC Level 26813.14.4 ESD Immunity Test – ATE Stage 27113.15 Alternative ESD/EMC Scanning Methods 27113.15.1 Alternative ESD/EMC Scanning Methods – Printed Circuit Board 27113.15.2 Electromagnetic Interference (EMI) Emission Scanning Methodology 27413.15.3 Radio Frequency (RF) Immunity Scanning Methodology 27413.15.4 Resonance Scanning Methodology 27513.15.5 Current Spreading Scanning Methodology 27513.16 Current Reconstruction Methodology 27613.16.1 EOS and Residual Current 27613.16.2 Printed Circuit Board (PCB) Trace Electromagnetic Emissions 27613.16.3 Test Procedure and Sequence 27713.17 Printed Circuit Board (PCB) Design EMC Solutions 27713.18 Summary and Closing Comments 280Problems 281References 282A Glossary of Terms 284B Standards 288B. 1 ESD Association 288B. 2 International Organization of Standards 289B. 3 Iec 289B. 4 Rtca 289B. 5 Department of Defense 289B. 6 Military Standards 289B. 7 Airborne Standards and Lightning 290Index 291