ESD

Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.”  Voldman was a member of the semiconductor development of IBM, Qimonda, and Intersil and worked as a full time consultant for Taiwan Semiconductor Manufacturing Corporation (TSMC) and a consultant on latchup, for the Samsung Electronics Corporation. He initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally reaching over 40  universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, China and Senegal. He is a recipient of 252 issued US patents and has written over 150 technical papers. He has served as an expert witness in patent litigation; and has also founded a limited liability corporation (LLC) consulting business supporting patents, patent writing and patent litigation. Steven Voldman provides tutorials and lectures on inventions, innovations, and patents.Dr. Voldman is an author of the  book series including  ESD: Physics and Devices, ESD: Circuits and Devices, 2nd Edition of ESD: Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, Latchup, ESD: Failure Mechanisms and Models,  ESD: Design and Synthesis, ESD Basics: From Semiconductor Manufacturing to Product Use, and Electrical Overstress (EOS): Devices, Circuits and Systems, ESD: Analog Circuits and Design,, as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design andNanoelectronics: Nanowires, Molecular Electronics, and Nano-devices. In addition, the International Chinese editions of booksare also released.

• About the Author xixPreface xxiAcknowledgments xxv1 Electrostatic Discharge 11.1 Electricity and Electrostatic Discharge 11.1.1 Electricity and Electrostatics 11.1.2 Electrostatic Discharge 21.1.3 Key ESD Patents, Inventions, and Innovations 41.1.4 Table of ESD Defect Mechanisms 81.2 Fundamental Concepts of ESD Design 111.2.1 Concepts of ESD Design 121.2.2 Device Response to External Events 131.2.3 Alternate Current Loops 141.2.4 Switches 141.2.5 Decoupling of Current Paths 151.2.6 Decoupling of Feedback Loops 151.2.7 Decoupling of Power Rails 151.2.8 Local and Global Distribution 151.2.9 Usage of Parasitic Elements 161.2.10 Buffering 161.2.11 Ballasting 161.2.12 Unused Section of a Semiconductor Device, Circuit, or Chip Function 171.2.13 Impedance Matching between Floating and Nonfloating Networks 171.2.14 Unconnected Structures 171.2.15 Utilization of Dummy Structures and Dummy Circuits 171.2.16 Nonscalable Source Events 171.2.17 Area Efficiency 181.3 ESD, EOS, EMI, Electromagnetic Compatibility, and Latchup 181.3.1 Esd 181.3.2 Electrical Overstress 191.3.3 Electromagnetic Interference 191.3.4 Electromagnetic Compatibility 191.3.5 Latchup 191.4 ESD Models 191.4.1 Human Body Model 201.4.2 Machine Model 211.4.3 Cassette Model (Small Charge Model) 241.4.4 Charged Device Model 241.4.5 Transmission Line Pulse 251.4.6 Very Fast Transmission Line Pulse 261.5 ESD and System-Level Test Models 281.5.1 IEC 61000-4-2 291.5.2 Human Metal Model 291.5.3 IEC 61000-4-5 301.5.4 Charged Board Model 311.5.5 Cable Discharge Event 321.5.5.1 CDE and Scaling 361.5.5.2 CDE—Cable Measurement Equipment 371.5.5.3 Cable Configuration—Test Configuration 381.5.5.4 Cable Configuration—Floating Cable 381.5.5.5 Cable Configuration—Held Cable 381.5.5.6 CDE—Peak Current versus Charged Voltage 391.5.5.7 CDE—Plateau Current versus Charged Voltage 391.6 Time Constants 391.6.1 Characteristic Times 391.6.2 Electrostatic and Magnetostatic Time Constants 391.6.2.1 Charge Relaxation Time 391.6.2.2 Magnetic Diffusion Time 401.6.2.3 Electromagnetic Wave Transit Time 401.6.3 Thermal Time Constants 421.6.3.1 Heat Capacity 421.6.3.2 Thermal Diffusion 421.6.3.3 Heat Transport Equation 421.6.4 Thermal Physics Time Constants 431.6.4.1 Adiabatic, Thermal Diffusion Timescale, and Steady State 441.6.5 Semiconductor Device Time Constants 451.6.5.1 Depletion Region Transit Time 451.6.5.2 Silicon Diode Storage Delay Time 451.6.5.3 Bipolar Base Transit Time 461.6.5.4 Bipolar Turn-on Transient Time 461.6.5.5 Bipolar Turn-off Transient Time 461.6.5.6 Bipolar Emitter Transition Capacitance Charging Time 461.6.5.7 Bipolar Collector Capacitance Charging Time 471.6.5.8 SCR Time Response 471.6.5.9 MOSFET Transit Time 471.6.5.10 MOSFET Drain Charging Time 481.6.5.11 MOSFET Gate Charging Time 481.6.5.12 MOSFET Parasitic Bipolar Response Time 481.6.6 Circuit Time Constants 491.6.6.1 Pad Capacitance 491.6.6.2 Half-Pass TGs 491.6.6.3 N-Channel Half-Pass Transistor Charging Time Constant 491.6.6.4 Half-pass Transistor TG Discharge Time Constant 491.6.6.5 P-Channel Half-Pass Transistor Charging Time Constant 491.6.6.6 Inverter Propagation Delay Time Constants 501.6.6.7 High-to-Low and Low-to-High Transition Time 501.6.6.8 Inverter Propagation Delay Time 511.6.6.9 Series N-channel MOSFETs Discharge Delay Time 511.6.6.10 Series P-channel MOSFETs Charge Delay Time 511.6.7 Chip-Level Time Constants 521.6.7.1 Peripheral I/O Power Bus Time Constant 521.6.7.2 Core Chip Time Constant 531.6.7.3 Substrate Time Constants 531.6.7.4 Package Time Constants 541.6.8 ESD Time Constants 541.6.8.1 ESD Events 551.6.8.2 HBM Characteristic Time 551.6.8.3 mm Characteristic Time 561.6.8.4 CDM Characteristic Time 571.6.8.5 Charged Cable Model Characteristic Time 571.6.8.6 CDE Model 571.6.8.7 CCM Characteristic Time 581.6.8.8 TLP Model Characteristic Time 581.6.8.9 VF-TLP Model Characteristic Time 591.7 Capacitance, Resistance, and Inductance and ESD 591.7.1 The Role of Capacitance 591.7.2 The Role of Resistance 601.7.3 The Role of Inductance 611.8 Rules of Thumb and ESD 621.8.1 ESD Design: An “ESD Ohm’s Law”—A Simple ESD Rule-of-Thumb Design Approach 621.9 ESD Scaling 631.10 Lumped versus Distributed Analysis and ESD 651.10.1 Current and Voltage Distributions 651.10.2 Lumped versus Distributed Systems 661.10.3 Distributed Systems—Ladder Network Analysis 671.10.4 RLC Distributed Systems 691.10.5 Resistor–Capacitor (RC) Distributed Systems 741.10.6 RG Distributed Systems 771.11 ESD Metrics: Chip-Level ESD Metrics and Figures of Merit 791.11.1 Chip Mean Pin Power-to-Failure 801.11.2 Chip Pin Standard Deviation Power-to-Failure 801.11.3 Chip Mean Pin Power-to-Failure to ESD Specification Margin 801.11.4 Worst-Case Pin Power-to-Failure to Specification ESD Margin 811.11.5 Total ESD Area to Total Chip Area Ratio 811.11.6 ESD Area to I/O Area Ratio 811.11.7 Circuit ESD Metrics 821.11.7.1 Circuit ESD Protection Level to ESD Loading Effect 821.11.7.2 Circuit Performance to ESD Loading Effect 821.11.7.3 ESD Area to Total Circuit Area Ratio 831.11.7.4 Circuit ESD Level to Specification Margin 831.11.7.5 Device ESD Metric 831.12 ESD Quality and Reliability Business Metrics 841.13 Twelve Steps to Building an ESD Strategy 851.14 Summary and Closing Comments 86Problems 87References 872 Design Synthesis 942.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection 942.2 Electrical and Spatial Connectivity 952.2.1 Electrical Connectivity 952.2.2 Thermal Connectivity 952.2.3 Spatial Connectivity 962.3 ESD, Latchup, and Noise 962.3.1 Noise 972.3.2 Latchup 982.4 Interface Circuits and ESD Elements 982.5 ESD Power Clamp Networks 1012.5.1 Placement of ESD Power Clamps 1042.6 ESD Rail-to-Rail Networks 1052.6.1 Placement of ESD Rail-to-Rail Networks 1072.6.2 Peripheral and Array I/O 1072.7 Guard Rings 1092.8 Pads, Floating Pads, and No-connect Pads 1112.9 Structures under Bond Pads 1122.10 Mixed Signal Architecture: CMOS 1122.10.1 Digital and Analog CMOS Architecture 1142.10.2 Digital and Analog Floor Plan: Placement of Analog Circuits 1142.11 MS Architecture: Digital, Analog, and RF Architecture 1162.12 Digital-to-Analog Interdomain Signal Line Failures 1182.12.1 Digital-to-Analog Core Spatial Isolation 1202.12.2 Digital-to-Analog Core Ground Coupling 1202.12.3 Digital-to-Analog Core Resistive Ground Coupling 1202.12.4 Digital-to-Analog Core Diode Ground Coupling 1202.12.5 Domain-to-Domain Signal Line ESD Networks 1222.12.6 Domain-to-Domain Third-Party Coupling Networks 1222.12.7 Domain-to-Domain Cross-Domain ESD Power Clamp 1232.13 Summary and Closing Comments 124Problems 124References 1253 MOSFET ESD Design 1293.1 Basic ESD Design Concepts 1293.2 ESD MOSFET Design: Channel Length 1363.2.1 Channel Length and Linewidth Control 1363.2.2 ACLV Control 1383.2.3 MOSFET ESD Design Practices 1423.3 N-Channel MOSFET Design: Channel Width 1433.4 ESD MOSFET Design: Contacts 1443.4.1 Gate-to-Contact Spacing 1443.4.1.1 Off-Axis Current Distribution 1483.4.1.2 Self-Heating Equienergy Contours 1483.4.2 Contact-to-Contact Space 1493.4.3 ESD Design: End Contact 1523.4.4 ESD MOSFET Design: Contacts to Isolation Edge 1533.5 ESD MOSFET Design: Metal Distribution 1533.5.1 MOSFET Metal Bus Design and Current Distribution 1533.5.2 MOSFET Ladder Network Model 1543.5.3 MOSFET Wiring: Parallel Current Distribution 1583.5.4 MOSFET Wiring: Antiparallel Current Distribution 1623.6 ESD MOSFET Design: Silicide Masking 1653.6.1 ESD MOSFET Design: Silicide Mask Design 1653.6.2 ESD MOSFET Design: Silicide Mask Design over Source and Drain 1663.6.3 ESD MOSFET Design: Silicide Mask Design over Gate 1673.7 ESD MOSFET Design: Series Cascode Configurations 1703.7.1 MOSFET ESD Design: Series Cascode MOSFET 1703.7.2 Integrated Cascoded MOSFETs 1713.8 ESD MOSFET Design: Multifinger MOSFET Design—Integration of Coupling and Ballasting Techniques 1743.8.1 Grounded-Gate Resistor-Ballasted MOSFET 1743.8.2 Soft Substrate Grounded-Gate Resistor-Ballasted MOSFET 1763.8.3 Gate-Coupled Domino Resistor-Ballasted MOSFET 1773.8.4 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with MOSFET 1793.8.5 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with Diode 1803.9 ESD MOSFET Design: Enclosed Drain Design Practice 1813.10 ESD MOSFET Interconnect Ballasting Design 1823.11 ESD MOSFET Design: Source and Drain Segmentation 1843.12 MOSFET Design for Analog Applications 1853.13 Summary and Closing Comments 187Problems 187References 1884 ESD Design: Diode Design 1914.1 ESD Diode Design: ESD Basics 1914.1.1 Basic ESD Design Concepts 1914.1.2 ESD Diode Design: ESD Diode Operation 1934.2 ESD Diode Anode Design 1944.2.1 P+ Diffusion Anode Width Effect 1954.2.2 P+ Anode Contacts 1954.2.3 P+ Anode Silicide to Edge Design 1954.2.4 P+ Anode to N+ Cathode Isolation Spacing 1984.2.5 P+ Anode Diode End Effects 1984.2.6 Circular and Octagonal ESD Diode Design 2004.3 ESD Diode Design: Interconnect Wiring 2024.3.1 Parallel Wiring Design 2034.3.2 Antiparallel Wiring Design 2034.3.3 Quantized Tapered Parallel and Antiparallel Wiring 2034.3.4 Continuous Tapered Antiparallel and Parallel Wiring 2034.3.5 Perpendicular (and Broadside) Wiring with Center-Fed Design 2054.3.6 Perpendicular (and Broadside) with Uniform Metal Width 2064.3.7 Perpendicular (and Broadside) Wiring with T-Shaped Extensions 2074.3.8 Metal Design for Structures under Bond Pads 2084.4 ESD Design: Polysilicon-Bound Diode Designs 2104.4.1 ESD Design Issues with Polysilicon-Bound Diode Structures 2124.5 N-Well Diode Design 2134.5.1 N-Well Diode Wiring Design 2134.5.2 N-Well Contact Density 2144.5.3 N-Well ESD Design, Guard Rings, and Adjacent Structures 2144.6 N+/P Substrate Diode Design 2164.7 ESD Design: Diode String Design 2174.7.1 ESD Design: Diode String Design—Architecture 2234.7.2 Diode String Elements in Multiple I/O Environments 2234.7.3 Integration of Signal Pads 2244.7.4 ESD Design: Diode String Design—Darlington Amplification 2274.7.5 ESD Design: Diode String Design—Area Scaling 2294.8 Triple-Well ESD Diode Design 2314.9 Summary and Closing Comments 234Problems 234References 2365 ESD Design: Passive Resistors 2395.1 N-Well Resistors 2395.1.1 N-Well ESD Design Issues 2395.1.2 N-Well Resistors ESD Design Issues: Integration with MOSFETs 2435.1.3 N-Well Resistor Ballasting Design 2455.2 N-Diffusion Resistor Design 2485.2.1 N-Diffusion Resistors for ESD Protection 2485.2.2 N-Diffusion Resistors Ballasting Design 2495.3 P-Diffusion Resistor Design 2525.3.1 P-Diffusion Resistors for ESD Protection 2535.4 Br 2545.4.1 BR Design 2545.4.2 BR as an ESD Diode Element 2565.4.3 BR as an ESD HBM and CDM Element 2575.4.4 BR Ballasting 2605.4.5 BR Design Integration and ESD 2615.4.6 BR: Current Robbing and Balancing ESD and Resistor Parasitics 2635.4.7 BR-to-BR ESD Failure Mechanisms 2665.4.8 BR Gate Connection and Failure Mechanisms 2675.5 Summary and Closing Comments 268Problems 268References 2706 Passives for Digital, Analog, and RF Applications 2716.1 Analog Design Layout Revisited 2716.1.1 Analog Design: Local Matching 2726.1.2 Analog Design: Global Matching 2726.1.3 Symmetry 2736.1.4 Layout Design Symmetry 2736.1.5 Thermal Symmetry 2736.2 Common Centroid Design 2746.2.1 Common Centroid Arrays 2746.2.2 One-Axis Common Centroid Design 2756.2.3 Two-Axis Common Centroid Design 2756.3 Interdigitation Design 2756.4 Common Centroid and Interdigitation Design 2766.5 Passive Element Design 2776.6 Resistor Element Design 2776.6.1 Resistor Element Design: Dogbone Layout 2776.6.2 Resistor Design: Analog Interdigitated Layout 2786.6.3 Dummy Resistor Layout 2786.6.4 Thermoelectric Cancellation Layout 2796.6.5 Electrostatic Shield 2806.6.6 Interdigitated Resistors and ESD Parasitics 2816.7 Capacitor Element Design 2836.8 Inductor Element Design 2836.9 Summary and Closing Comments 286Problems 286References 2867 Off-Chip Drivers and ESD 2887.1 Off-chip Drivers 2887.1.1 OCD I/O Standards and ESD 2897.1.2 OCD ESD Design Basics 2907.1.3 OCD: CMOS Asymmetric Pull-Up/Pull-Down 2917.1.4 OCD: CMOS Symmetric Pull-Up/Pull-Down 2927.1.5 OCD: Gunning Transceiver Logic 2947.1.6 OCD: High-Speed Transceiver Logic 2957.1.7 OCD: Stub Series-Terminated Logic 2967.2 OCDs: mvi 2977.3 OCDs: Self-Bias Well OCD Networks 2977.3.1 Self-Bias Well OCD Networks 2977.3.2 ESD Protection Networks for Self-Bias Well OCD Networks 3007.4 Programmable Impedance OCD Network 3027.4.1 OCD: PIMP OCD Networks 3027.4.2 ESD Input Protection Networks for PIMP OCDs 3057.5 OCDs: Universal OCDs 3057.6 OCDs: Gate-Array OCD Design 3067.6.1 Gate-Array OCD ESD Design Practices 3067.6.2 Gate-Array OCD Design—Usage of Unused Elements 3067.6.3 Gate-Array OCD Design—Impedance Matching of Unused Elements 3077.6.4 OCD ESD Design—Power Rails Over Multifinger MOSFETs 3087.7 OCDs: Gate-Modulated Networks 3097.7.1 OCD: Gate-Modulated MOSFET ESD Network 3097.7.2 OCD Simplified Gate-Modulated Network 3107.8 OCDs ESD Design: Integration of Coupling and Ballasting Techniques 3117.8.1 Ballasting and Coupling 3117.8.2 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with Diode 3117.8.3 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with an MOSFET 3127.8.4 Gate-Coupled Domino Resistor-Ballasted MOSFET 3147.9 Substrate-Modulated Resistor-Ballasted MOSFET 3157.10 Summary and Closing Comments 317Problems 318References 3198 Receiver Circuits 3228.1 Receivers and ESD 3228.1.1 Receivers and Receiver Delay Time 3238.1.2 ESD Loading Effect on Receiver Performance 3238.2 Receivers and ESD 3248.2.1 Receivers and HBM 3248.2.2 Receivers and CDM 3258.3 Receivers and Receiver Evolution 3278.3.1 Receiver Circuits with Half-Pass TG 3278.3.2 Receiver with Full-Pass TG 3308.3.3 Receiver, Half-Pass TG, and Keeper Network 3328.3.4 Receiver, Half-Pass TG, and the Modified Keeper Network 3358.4 Receiver Circuits with Pseudozero V T Half-Pass TG 3378.5 Receiver with ZVT TG 3398.6 Receiver Circuits with Bleed Transistors 3428.7 Receiver Circuits with Test Functions 3438.8 Receiver with Schmitt Trigger Feedback Network 3448.9 Bipolar Transistor Receivers 3478.9.1 Bipolar Single-Ended Receiver Circuits 3478.10 Differential Receivers 3498.10.1 Signal Differential Receiver 3508.10.2 Signal CMOS Differential Receivers 3508.10.3 Signal Bipolar Differential Receivers 3508.11 CMOS Differential Receiver with Analog Layout Concepts 3558.11.1 CMOS Differential Receiver Capacitance Loading 3558.11.2 CMOS Differential Receiver ESD Mismatch 3568.11.3 Analog Differential Pair ESD Signal Pin Matching with Common Well Layout 3598.11.4 Analog Differential Pair Common Centroid Design Layout: Signal Pin-to-Signal Pin and Parasitic ESD Elements 3598.12 Summary and Closing Comments 363Problems 364References 3669 Silicon on Insulator (SOI) ESD Design 3689.1 Silicon on Insulator ESD Design Concepts 3689.2 SOI Design MOSFET with Body Contact: T-Shape Layout Style 3729.3 SOI Lateral Diode Structure 3759.3.1 Transistors: Bulk Versus SOI Technology 3759.3.2 SOI Lateral Diode Design 3769.3.3 SOI Lateral Diode Perimeter Design 3769.3.4 SOI Lateral Diode Channel Length Design 3779.3.5 SOI Lateral P+/N−/N+ Diode Structure 3779.3.6 SOI Lateral P+/P−/N+ Diode Structure 3779.3.7 SOI Lateral P+/P−/N−/N+ Diode Structure 3789.3.8 SOI Lateral Ungated P+/P−/N−/N+ Diode Structure 3799.3.9 SOI Lateral Diode Structures and SOI MOSFET Halos 3799.4 SOI BR Elements 3809.5 Dynamic Threshold SOI MOSFET 3819.6 SOI Dual-Gate MOSFET 3849.7 SOI ESD Design: Mixed Voltage T-Shape Layout Style 3849.8 SOI ESD Design: Mixed Voltage Diode Strings 3849.9 SOI ESD Design: Double-Diode Network 3859.10 Bulk to SOI ESD Design Remapping 3879.11 SOI ESD Design in MVI Environments 3919.12 Comparison of Bulk to SOI ESD Results 3939.13 SOI ESD Design with Aluminum Interconnects 3949.14 SOI ESD Design with Copper Interconnects 3959.15 SOI ESD Design with Gate Circuitry 3979.16 SOI FinFET Structure 3999.17 Summary and Closing Comments 403Problems 403References 40510 ESD Circuits: BiCMOS 40810.1 Bipolar ESD Input Circuits 40810.2 Diode-Configured Bipolar ESD Input Circuits 41210.3 Bipolar ESD Input Circuits: Voltage-Triggered Elements 41310.3.1 Voltage Triggered Bipolar ESD Input Circuits Classifications 41310.3.2 Bipolar ESD Input: Resistor Grounded-Base ESD Input 41410.3.3 Bipolar ESD Input Circuits: Zener Breakdown Voltage Triggered 41810.3.4 Bipolar ESD: BV CEO Voltage-Triggered ESD Input 42310.3.5 Bipolar ESD Input Circuits: Ultralow-Voltage Forward-Biased Voltage Trigger 43010.3.6 ESD Bipolar Input Circuits: Future Networks and Scaling 43310.3.7 Bipolar ESD Input Device Scaling 43610.4 BiCMOS Mixed Signal Designs 43710.5 Summary and Closing Comments 437Problems 437References 43811 ESD Power Clamps 44211.1 ESD Power Clamp Design Practices 44211.1.1 Classification of ESD Power Clamps 44411.1.2 Design Synthesis of ESD Power Clamp: Key Design Parameters 44611.2 Design Synthesis of ESD Power Clamps Trigger Networks 44611.2.1 Transient Response Frequency Trigger Element and the ESD Frequency Window 44611.2.2 The ESD Power Clamp Frequency Design Window 44711.2.3 Design Synthesis of ESD Power Clamp: Voltage-Triggered ESD Trigger Elements 44711.3 Design Synthesis of ESD Power Clamp: The ESD Power Clamp Shunting Element 44911.3.1 ESD Power Clamp Trigger Condition versus Shunt Failure 45011.3.2 ESD Clamp Element: Width Scaling 45011.3.3 ESD Clamp Element: On-Resistance 45111.3.4 ESD Clamp Element: Safe Operating Area 45111.4 ESD Power Clamp Issues 45211.4.1 ESD Power Clamp Issues: Power-Up and Power-Down 45211.4.2 ESD Power Clamp Issues: False Triggering 45211.4.3 ESD Power Clamp Issues: Precharging 45211.4.4 ESD Power Clamp Issues: Postcharging 45311.5 ESD Power Clamp Design 45311.5.1 Native Power Supply RC-Triggered MOSFET ESD Power Clamp 45311.5.2 Nonnative Power Supply RC-Triggered MOSFET ESD Power Clamp 45411.5.3 ESD Power Clamp Networks with Improved Inverter Stage Feedback 45411.5.4 ESD Power Clamp Design Synthesis: Forward-Bias-Triggered ESD Power Clamps 45611.5.5 ESD Power Clamp Design Synthesis: IEC 61000-4-2 Responsive ESD Power Clamps 45711.5.6 ESD Power Clamp Design Synthesis: Precharging and Postcharging Insensitive ESD Power Clamps 45711.6 Master/Slave ESD Power Clamp Systems 45811.7 Series-Stacked RC-Triggered ESD Power Clamps 46011.8 ESD Power Clamps: Triple-Well Series Diodes as Core Clamps 46011.9 Summary and Closing Comments 464Problems 465References 46612 Bipolar ESD Power Clamps 46812.1 Bipolar ESD Power Clamps 46812.2 Bipolar Voltage-Triggered ESD Power Clamps 46812.2.1 Bipolar ESD Power Clamp: Zener Breakdown Voltage Triggered 46912.2.2 Bipolar ESD Power Clamp: BV CEO Voltage-Triggered ESD Power Clamp 47012.3 ESD Power Clamp Design Synthesis: Bipolar ESD Power Clamps 47312.4 Mixed Voltage Interface Forward-Bias Voltage and BV CEO Breakdown Synthesized Bipolar ESD Power Clamps 47612.5 Ultralow-Voltage Forward-Biased Voltage-Trigger BiCMOS ESD Power Clamp 48012.6 Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance Triggered 48512.7 Summary and Closing Comments 485Problems 486References 48713 Silicon-Controlled Rectifier Power Clamps 48913.1 ESD Silicon-Controlled Rectifier Circuits 48913.1.1 Unidirectional SCR 48913.1.2 Bidirectional SCR ESD Power Clamps 48913.1.3 Medium-Level SCR ESD Power Clamps 49013.1.4 Low Voltage Triggered SCR ESD Power Clamps 49013.2 Lateral Diffused MOS Circuits 49213.2.1 LOCOS-Defined LDMOS 49213.2.2 Shallow Trench Isolation-Defined LDMOS 49313.2.3 STI-Defined Isolated LDMOS 49413.3 DeMOS Circuits 49613.3.1 DeNMOS 49713.3.2 DeNMOS-SCR Transistor 49713.4 Ultrahigh-Voltage LDMOS (UHV-LDMOS) Circuits 49713.4.1 Uhv-ldmos 49713.4.2 Uhv-ldmos-scr 49713.5 Summary and Closing Comments 501Problems 501References 501Glossary of Terms 504Standards 509Index 512