Integrated Circuit Design for Radiation Environments

STEPHEN J. GAUL is a Senior Principal Engineer at Renesas Electronics Americas, Inc., Florida, USA. He has worked in the semiconductor/integrated circuit field for over 35 years and has authored many papers and over 35 patents, many specific to radiation-hard/radiation-tolerant techniques. NICOLAAS VAN VONNO is currently a Principal Engineer at Renesas Electronics Americas, Inc., Florida, USA, and has been an independent consultant in the radiation effects field. He has been Guest Editor, Session Chairman, and Short Course Chairman for the IEEE Nuclear and Space Radiation Effects Conference (NSREC). STEVEN H. VOLDMAN, Ph.D., is a Consultant on ESD and latchup, as well as invention and patenting. He is a Fellow of the Electrical and Electronics Engineers (IEEE) and author of over 10 books and 262 patents. WESLEY H. MORRIS is President of Silicon-X (Technology focus), hardening CMOS devices to radiation and extreme temperatures. His career experience includes development of RH CMOS devices with SOS (RCA) and SOI (Harris), the first to prove bulk CMOS devices can be made latchup immune to extreme SEE radiation and operate reliably at high temperatures (250C). Morris is an author/inventor with multiple papers and patents related to RH and HT topics.

• About the Authors xiiiPreface xixAcknowledgments xxiiiGlossary of Terms xxv1 Introduction and Historical Perspective 11.1 Introduction 11.2 Discovery of X-Rays, Radiation, and Subatomic Particles 21.3 The Nuclear Age 81.4 The Space Age 91.5 Semiconductors – Revolution, Evolution, and Scaling 151.6 Beginning of Ionizing Radiation Effects in Semiconductors 201.7 Beginning of Single-Event Effects in Semiconductors 221.8 Summary and Closing Comments 26References 272 Radiation Environments 312.1 Introduction 312.2 X-Rays, Gamma Rays, and the Atom 312.2.1 X-Rays 312.2.2 X-Ray Absorption 342.2.3 Auger Electrons 362.2.4 Nuclear Structure and Binding Energy 362.2.4.1 Models of the Nucleus 382.2.5 Alpha and Beta Decay 502.2.5.1 Alpha Decay 512.2.5.2 Beta Decay 522.2.6 Gamma-Ray Emission or Gamma Decay 532.2.7 Other Types of Nuclear Radiation 542.3 Natural Radioactivity 552.3.1 Exponential Decay 552.3.2 Decay Series 562.4 The Space Environment 582.4.1 Solar Radiation 592.4.2 Trapped Radiation 622.4.3 Cosmic Rays 662.4.4 Atmospheric Neutrons 692.5 The Nuclear Reactor Environment 712.6 The Weapons Environment 752.7 The Environment in High-Energy Physics Facilities 782.8 Summary and Closing Comments 80References 813 Radiation Effects in Semiconductor Materials 853.1 Introduction 853.2 Basic Effects 863.2.1 Heavy Charged Particles 863.2.1.1 Stopping Power 863.2.1.2 Electronic Stopping 873.2.1.3 Nuclear Stopping 923.2.2 Electrons 933.2.2.1 Electromagnetic Radiation 933.2.2.2 Stopping Power 963.2.3 Neutrons 1013.2.3.1 Neutron Cross Section 1023.2.3.2 Interactions with Matter 1033.2.4 Photons (X-Rays, Gamma Rays) 1063.2.4.1 Photoelectric Effect 1073.2.4.2 Compton Scattering 1083.2.4.3 Pair Production 1093.2.4.4 Photonuclear Reactions 1103.3 Charge Trapping in Silicon Dioxide 1113.3.1 Charge Generation/Recombination 1113.3.1.1 Geminate and Columnar Models 1123.3.1.2 Geminate Recombination 1133.3.1.3 Columnar Recombination 1153.3.1.4 Numerical Methods 1173.3.2 Hole Trapping and Transport 1183.3.2.1 E′ Centers 1203.3.2.2 Continuous-Time Random-Walk (CTRW) 1223.3.3 The Silicon/Silicon Dioxide Interface 1243.3.3.1 Interface Traps 1253.3.3.2 Border Traps 1273.3.3.3 Hydrogen 1283.3.3.4 ELDRS 1303.4 Bulk Damage 1313.5 Summary and Closing Comments 133References 1354 Radiation-Induced Single Events 1434.1 Introduction – Single-Events Effects (SEE) 1434.1.1 Single-Event Upsets (SEU) 1434.1.2 Multiple-Bit Upset (MBU) 1434.1.3 Single-Event Transients (SET) 1444.1.4 Single-Event Functional Interrupts (SEFIs) 1444.1.5 Single-Event Disturb (SED) 1454.1.6 Single-Event Snapback (SESB) 1464.1.7 Single-Event Latchup (SEL) 1464.1.8 Single-Event Burnout (SEB) 1464.1.9 Single-Event Gate Rupture (SEGR) 1474.1.10 Single-Event Hard Errors (SHE) 1474.2 Single-Event Upset (SEU) 1484.2.1 SEU – Memory 1484.2.2 SEU in CMOS Memory 1484.2.3 SEU in Bipolar Memory 1484.2.4 SEU in CMOS SRAM 1494.2.5 SEU in Future Technology – FINFETs 1494.3 SEU – Particle Sources 1494.3.1 SEU Source – Alpha Particles 1504.3.2 SEU Source – Pions and Muons 1524.3.3 SEU – Neutrons 1534.3.4 SEU Source – Protons 1534.3.5 SEU – Heavy Ions 1544.4 Single-Event Gate Rupture (SEGR) 1544.4.1 Definition SEGR 1554.4.2 SEGR Source – Ion Track 1554.4.3 SEGR Source – Failure Mechanism 1564.4.4 SEGR – Modeling and Simulation 1564.4.5 Power Transistors and SEGR 1564.4.5.1 Lateral Power Transistors SEGR 1564.4.5.2 Vertical MOS (VMOS) SEGR 1574.4.5.3 Advanced Technologies – Planar MOSFET SEGR 1574.5 Single-Event Transients (SETs) 1584.5.1 SET Definition 1584.5.2 SET Source 1584.5.3 SET Source Failure Mechanisms 1594.5.4 SET in Integrated Circuits 1594.5.4.1 Digital Circuitry 1594.5.4.2 Continuous Time Analog Circuitry 1594.5.5 Prediction and Hardening 1594.6 Single-Event Latchup (SEL) 1594.6.1 SEL Definition 1604.6.2 SEL Source 1604.6.3 SEL Time Response 1614.6.4 SEL Maximum Charge Collection Evaluation in a Parallelepiped Region 1624.6.5 A SEL Design Practice 1644.6.6 SEL Semiconductor Device Simulation 1654.7 Summary and Closing Comments 165References 1665 Radiation Testing 1735.1 Introduction 1735.1.1 Radiation Units and Measurements 1735.2 Radiation Testing and Sources 1755.2.1 Total Ionizing Dose (TID) Testing 1765.2.2 Total Ionizing Dose (TID) Sources 1795.2.3 Single-Event Effects (SEE) Testing 1825.2.4 Single-Event Effects (SEE) Sources and Facilities 1875.2.5 Neutron Testing 1925.2.6 Neutron Sources 1935.2.7 Proton Testing 1955.2.8 Proton Sources 1965.2.9 Transient Gamma Testing 1975.2.10 Transient Gamma Sources 1985.3 Summary and Closing Comments 201References 2046 Device Modeling and Simulation Techniques 2096.1 Introduction 2096.2 Device Modeling 2106.2.1 Circuit Simulators 2116.2.2 Intrinsic Models 2126.2.3 Composite Models and Inline Subcircuits 2126.2.4 Analysis and Statistics Programs 2146.3 Radiation Effects on Semiconductor Devices 2156.3.1 MOS Capacitors and Transistors 2156.3.1.1 MOS Capacitors 2166.3.1.2 MOS Transistors 2196.3.2 Diodes and Bipolar Transistors 2246.3.2.1 Diodes 2246.3.2.2 Bipolar Transistors 2256.3.3 Power Devices 2306.3.3.1 DMOS Composite Models 2316.3.3.2 Operating Voltage 2326.3.4 Other Devices 2326.3.4.1 Junction Field Effect Transistors (JFETs) 2326.3.4.2 Resistors 2346.3.4.3 Capacitors 2356.3.5 Some Modeling Challenges 2356.4 Circuit Simulation 2366.4.1 Corner Simulation 2366.4.2 SEE Simulation 2396.5 Summary and Closing Comments 242References 2447 Radiation Semiconductor Process and Layout Solutions 2497.1 Introduction 2497.2 Substrate Hardened Technologies 2497.2.1 Silicon-on-Insulator (SOI) Technologies 2507.2.1.1 Separation by Implanted Oxygen (SIMOX) 2507.2.1.2 Silicon-Bonded (SIBOND) Technology 2507.2.2 Silicon on Sapphire (SOS) 2517.2.3 Silicon on Diamond (SOD) 2527.2.4 Silicon on Nothing (SON) 2527.3 Oxide Hardening Technologies 2537.3.1 Oxide Growth and Fluorination of Oxide 2537.3.2 MOSFET Gate Oxide Hardening 2537.3.3 Recessed Oxide (ROX) Hardening 2547.3.4 LOCOS Isolation Hardening 2547.3.5 Shallow Trench Isolation (STI) Hardening 2547.4 CMOS Latchup Process Solutions 2557.5 CMOS Substrates – High-Resistance Substrates 2557.5.1 50Ω-cm Substrate Resistance 2597.6 Wells 2607.6.1 Single Well – Diffused N-Well 2617.6.2 Single Well – Retrograde N-Well 2617.6.3 Dual-Well Technology 2627.6.3.1 P-well and P++ Substrate 2627.6.3.2 P-Well and P+ Connecting Implant 2637.7 Triple-Well Technology 2647.7.1 Triple Well – Full Separation of Wells 2647.7.2 Triple Well – Merged Triple Well 2657.7.3 Triple Well – Merged Triple Well with Blanket Implant 2667.8 Sub-Collectors 2667.8.1 Epitaxial Grown Sub-Collector 2667.8.2 Implanted Sub-Collector 2677.8.3 Sub-Collector – NPN and PNP Bipolar Current Gain 2677.8.4 Sub-Collector – Beta Product 𝛽PNP𝛽NPN 2677.9 Heavily Doped Buried Layers (HDBL) 2687.9.1 Buried Implanted Layer for Lateral Isolation (BILLI) Process 2687.9.2 Continuous HDBL Implant 2687.9.3 Buried Guard Ring (BGR) 2707.10 Isolation Concepts 2707.10.1 LOCOS Isolation 2707.10.2 Shallow Trench Isolation (STI) 2707.10.3 Dual Depth Isolation 2717.10.4 Trench Isolation (TI) 2727.10.4.1 Trench Isolation (TI) and Sub-Collector 2747.11 Deep Trench 2777.11.1 Deep Trench (DT) within PNPN Structure 2797.11.2 Deep Trench Structure and Sub-Collector 2817.11.3 Deep Trench Structure and Merged Triple Well 2837.12 Layout Solutions 2847.12.1 Polysilicon Bound Structures 2847.12.2 Parasitic Isolation Device (PID) 2847.13 Summary and Closing Comments 286References 2878 Single-Event Upset Circuit Solutions 2938.1 Introduction 2938.2 CMOS DRAM SEU Circuit Solutions 2938.2.1 CMOS DRAM Redundancy 2948.2.2 CMOS DRAM with SRAM Error Correction 2948.3 CMOS SRAM SEU Circuit Solution 2968.3.1 CMOS SRAM Four-Device Cell 2968.3.2 CMOS SRAM Six-Device Cell 2978.3.3 CMOS SRAM 12-Device Cell 2988.4 Bipolar SRAM 2998.4.1 Bipolar SRAM Cell with Resistor Loads 3008.4.2 Bipolar SRAM Cell with Resistor Loads and Schottky Clamps 3008.4.3 Bipolar SRAM Cell with PNP Transistors 3018.5 Bipolar SRAM Circuit Solutions 3018.6 SEU in CMOS Logic Circuitry 3028.7 Summary and Closing Comments 302References 3039 Latchup Circuit Solutions 3059.1 Introduction 3059.2 Power Supply Concepts 3059.2.1 Power Supply Current Limit – Series Resistor 3059.2.2 Power Supply Current Limit – Current Source 3069.2.3 Power Supply Solutions – Voltage Regulator 3079.2.4 Latchup Circuit Solutions – Power Supply Decoupling 3089.3 Overshoot and Undershoot Clamp Networks 3119.3.1 Passive Clamp Networks 3129.3.2 Active Clamp Networks 3139.3.3 Dynamic Threshold Triple Well Passive and Active Clamp Networks 3169.4 Passive and Active Guard Rings 3189.4.1 Passive Guard Ring Circuits and Structures 3189.4.2 Active Guard Ring Circuits and Structures 3199.5 Triple-Well Noise and Latchup Suppression Structures 3269.6 System-Level Latchup Issues 3269.7 Summary and Closing Comments 327References 32910 Emerging Effects and Future Technology 33310.1 Introduction 33310.2 Radiation Effects in Advanced Technologies 33310.2.1 Moore’s Law, Scaling, and Radiation Effects 33410.2.2 Technology Lifetime and Reliability 33410.2.2.1 New Missions 33510.2.2.2 Throwaway Mentality 33510.2.2.3 New Space Entrants 33510.2.3 Terrestrial Issues 33510.2.4 Space Mission Issues 33510.2.5 Server Farms 33510.2.6 Automotive 33610.2.7 Internet of Things (IoT) 33610.2.8 More than Moore 33610.3 Radiation Effects in Semiconductor Nanostructures 33610.3.1 Planar MOSFETs in Sub-25 nm 33710.3.2 Bulk FinFET 33810.3.3 SOI FinFET 33910.3.4 3-D Circuits 34010.4 Radiation Effects and Advanced Packaging 34010.4.1 Radiation Effects and 2.5-D Circuits and Technology 34110.4.2 Radiation Effects and 3-D Circuits and Technology 34110.4.3 More than Moore and 3-D Integration 34210.5 Ruggedized Capability 34210.5.1 Ruggedized Capability for Radiation 34310.5.2 Ruggedized Capability for High Temperature 34310.6 Radiation Models 34310.7 A Nuclear World 34410.8 Summary and Closing Comments 344References 345Index 347