John P. Hayes - Böcker

The third edition of "Computer Architecture and Organization" features a comprehensive updating of the material - especially case studies, worked examples, and problem sets - while retaining the book's time-proven emphasis on basic principles. Reflecting the dramatic changes in computer technology that have taken place over the last decade, the treatment of performance-related topics such as pipelines, caches, and RISC's has been expanded. Many examples and end-of-chapter problems have also been added.

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Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob­ lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.

The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication. Since the number of components in modem ICs is enormous, computer­ aided-design (CAD) programs are required to automate the difficult layout process. Prior CAD methods are inexact or limited in scope, and produce layouts whose area, and consequently manufacturing costs, are larger than necessary. This book addresses the problem of minimizing exactly the layout area of an important class of basic IC structures called CMOS cells. First, we precisely define the possible goals in area minimization for such cells, namely width and height minimization, with allowance for area-reducing reordering of transistors. We reformulate the layout problem in terms of a graph model and develop new graph-theoretic concepts that completely characterize the fundamental area minimization problems for series-parallel and nonseries-parallel circuits. These concepts lead to practical algorithms that solve all the basic layout minimization problems exactly, both for a single cell and for a one-dimensional array of such cells. Although a few of these layout problems have been solved or partially solved previously, we present here the first complete solutions to all the problems of interest.

Although bats are often thought of as cave dwellers, many species depend on forests for all or part of the year. Of the 45 species of bats in North America, more than half depend on forests, using the bark of trees, tree cavities, or canopy foliage as roosting sites. Over the past two decades it has become increasingly clear that bat conservation and management are strongly linked to the health of forests within their range. Initially driven by concern for endangered species-the Indiana bat, for example-forest ecologists, timber managers, government agencies, and conservation organizations have been altering management plans and silvicultural practices to better accommodate bat species. Bats in Forests presents the work of a variety of experts who address many aspects of the ecology and conservation of bats. The chapter authors describe bat behavior, including the selection of roosts, foraging patterns, and seasonal migration as they relate to forests. They also discuss forest management and its influence on bat habitat. Both public lands and privately owned forests are considered, as well as techniques for monitoring bat populations and activity.The important role bats play in the ecology of forests-from control of insects to nutrient recycling-is revealed by a number of authors. Bat ecologists, bat conservationists, forest ecologists, and forest managers will find in this book an indispensable synthesis of the topics that concern them.

Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob­ lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.

The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication. Since the number of components in modem ICs is enormous, computer­ aided-design (CAD) programs are required to automate the difficult layout process. Prior CAD methods are inexact or limited in scope, and produce layouts whose area, and consequently manufacturing costs, are larger than necessary. This book addresses the problem of minimizing exactly the layout area of an important class of basic IC structures called CMOS cells. First, we precisely define the possible goals in area minimization for such cells, namely width and height minimization, with allowance for area-reducing reordering of transistors. We reformulate the layout problem in terms of a graph model and develop new graph-theoretic concepts that completely characterize the fundamental area minimization problems for series-parallel and nonseries-parallel circuits. These concepts lead to practical algorithms that solve all the basic layout minimization problems exactly, both for a single cell and for a one-dimensional array of such cells. Although a few of these layout problems have been solved or partially solved previously, we present here the first complete solutions to all the problems of interest.

Quantum Circuit Simulation covers the fundamentals of linear algebra and introduces basic concepts of quantum physics needed to understand quantum circuits and algorithms. It requires only basic familiarity with algebra, graph algorithms and computer engineering. After introducing necessary background, the authors describe key simulation techniques that have so far been scattered throughout the research literature in physics, computer science, and computer engineering. Quantum Circuit Simulation also illustrates the development of software for quantum simulation by example of the QuIDDPro package, which is freely available and can be used by students of quantum information as a "quantum calculator."

Logic circuits are becoming increasingly susceptible to probabilistic behavior caused by external radiation and process variation. In addition, inherently probabilistic quantum- and nano-technologies are on the horizon as we approach the limits of CMOS scaling. Ensuring the reliability of such circuits despite the probabilistic behavior is a key challenge in IC design---one that necessitates a fundamental, probabilistic reformulation of synthesis and testing techniques. This monograph will present techniques for analyzing, designing, and testing logic circuits with probabilistic behavior.

Quantum Circuit Simulation covers the fundamentals of linear algebra and introduces basic concepts of quantum physics needed to understand quantum circuits and algorithms. It requires only basic familiarity with algebra, graph algorithms and computer engineering. After introducing necessary background, the authors describe key simulation techniques that have so far been scattered throughout the research literature in physics, computer science, and computer engineering. Quantum Circuit Simulation also illustrates the development of software for quantum simulation by example of the QuIDDPro package, which is freely available and can be used by students of quantum information as a "quantum calculator."