Saraju P. Mohanty – författare

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies.  The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level.  At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation.The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including: • Power Reduction Fundamentals• Energy or Average Power Reduction• Peak Power Reduction• Transient Power Reduction• Leakage Power ReductionLow-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits.

Brain Computer Interface: EEG Signal Processing discusses electroencephalogram (EEG) signal processing using effective methodology and algorithms. This book provides a basic introduction to EEG and a classification of different components present in EEG. It also helps the reader to understand the scope of processing EEG signals and their associated applications. Further, it covers specific aspects such as epilepsy detection; exploitation of P300 for various applications; design of an EEG acquisition system; and detection of saccade, fix, and blink from EEG and EOG data.Key Features: Explains the basis of brain computer interface and how it can be established using different EEG signal characteristics Covers the detailed classification of different types of EEG signals with respect to their physical characteristics Explains detection and diagnosis of epileptic seizures from the EEG data of a subject Reviews the design and development of a low-cost and robust EEG acquisition system Provides mathematical analysis of EEGs, including MATLAB® codes for students to experiment with EEG dataThis book is aimed at graduate students and researchers in biomedical, electrical, electronics, communication engineering, healthcare, and cyber physical systems.

Brain Computer Interface: EEG Signal Processing discusses electroencephalogram (EEG) signal processing using effective methodology and algorithms. This book provides a basic introduction to EEG and a classification of different components present in EEG. It also helps the reader to understand the scope of processing EEG signals and their associated applications. Further, it covers specific aspects such as epilepsy detection; exploitation of P300 for various applications; design of an EEG acquisition system; and detection of saccade, fix, and blink from EEG and EOG data.Key Features: Explains the basis of brain computer interface and how it can be established using different EEG signal characteristics Covers the detailed classification of different types of EEG signals with respect to their physical characteristics Explains detection and diagnosis of epileptic seizures from the EEG data of a subject Reviews the design and development of a low-cost and robust EEG acquisition system Provides mathematical analysis of EEGs, including MATLAB® codes for students to experiment with EEG dataThis book is aimed at graduate students and researchers in biomedical, electrical, electronics, communication engineering, healthcare, and cyber physical systems.

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies.  The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level.  At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation.The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including: • Power Reduction Fundamentals• Energy or Average Power Reduction• Peak Power Reduction• Transient Power Reduction• Leakage Power ReductionLow-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits.

This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.

This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.

Although existing nanometer CMOS technology is expected to remain dominant for the next decade, new non-classical devices are being developed as the potential replacements of silicon CMOS, in order to meet the ever-present demand for faster, smaller, more efficient integrate circuits.Many new devices are based on novel emerging materials such as one-dimensional carbon nanotubes and two-dimensional graphene, non-graphene two-dimensional materials, and transition metal dichalcogenides. Such devices use on/off operations based on quantum mechanical current transport, and so their design and fabrication require an understanding of the electronic structures of materials and technologies. Moreover, new electronic design automation (EDA) tools and techniques need to be developed based on integrating devices from emerging novel material-based technologies.The aim of this book is to explore the materials and design requirements of these emerging integrated circuit technologies, and to outline their prospective applications. It will be useful for academics and research scientists interested in future directions and developments in design, materials and applications of novel integrated circuit technologies, and for research and development professionals working at the cutting edge of integrated circuit development.

IP Core Protection and Hardware-Assisted Security for Consumer Electronics presents established and novel solutions for security and protection problems related to IP cores (especially those based on DSP/multimedia applications) in consumer electronics. The topic is important to researchers in various areas of specialization, encompassing overlapping topics such as EDA-CAD, hardware design security, VLSI design, IP core protection, optimization using evolutionary computing, system-on-chip design and application specific processor/hardware accelerator design.The book begins by introducing the concepts of security, privacy and IP protection in information systems. Later chapters focus specifically on hardware-assisted IP security in consumer electronics, with coverage including essential topics such as hardware Trojan security, robust watermarking, fingerprinting, structural and functional obfuscation, encryption, IoT security, forensic engineering based protection, JPEG obfuscation design, hardware assisted media protection, PUF and side-channel attack resistance.

The demand for ever smaller and portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturization. To enable even smaller electronics, various nanodevices including carbon nanotube transistors, graphene transistors, tunnel transistors and memristors (collectively called post-CMOS devices) are emerging that could replace the traditional and ubiquitous silicon transistor. This book explores these nanoelectronics at the device level including modelling and design.Topics covered include high-k dielectrics; high mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays; anodic metal-insulator-metal (MIM) capacitors; graphene transistors; junction and doping free transistors; nanoscale gigh-k/metal-gate CMOS and FinFET based logic libraries; multiple-independent-gate nanowire transistors; carbon nanotubes for efficient power delivery; timing driven buffer insertion for carbon nanotube interconnects; memristor modeling; and neuromorphic devices and circuits.This book is essential reading for researchers, research-focused industry designers/developers, and advanced students working on next-generation electronic devices and circuits.