Saraju P. Mohanty – författare

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies.  The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level.  At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation.

The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including:

• Power Reduction Fundamentals

• Energy or Average Power Reduction

• Peak Power Reduction

• Transient Power Reduction

• Leakage Power Reduction

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits.

Brain Computer Interface: EEG Signal Processing discusses electroencephalogram (EEG) signal processing using effective methodology and algorithms. This book provides a basic introduction to EEG and a classification of different components present in EEG. It also helps the reader to understand the scope of processing EEG signals and their associated applications. Further, it covers specific aspects such as epilepsy detection; exploitation of P300 for various applications; design of an EEG acquisition system; and detection of saccade, fix, and blink from EEG and EOG data.

Key Features:

This book is aimed at graduate students and researchers in biomedical, electrical, electronics, communication engineering, healthcare, and cyber physical systems.

Brain Computer Interface: EEG Signal Processing discusses electroencephalogram (EEG) signal processing using effective methodology and algorithms. This book provides a basic introduction to EEG and a classification of different components present in EEG. It also helps the reader to understand the scope of processing EEG signals and their associated applications. Further, it covers specific aspects such as epilepsy detection; exploitation of P300 for various applications; design of an EEG acquisition system; and detection of saccade, fix, and blink from EEG and EOG data.

Key Features:

This book is aimed at graduate students and researchers in biomedical, electrical, electronics, communication engineering, healthcare, and cyber physical systems.

This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.