Nano-CMOS and Post-CMOS Electronics

Saraju Mohanty is Professor at the Department of Computer Science and Engineering, University of North Texas, where he is the director of NanoSystem Design Laboratory (NSDL). His research interests focus on Energy-Efficient High-Performance Secure Electronic Systems. Prof. Mohanty is an inventor of 4 US patents, and an author of 200 peer-reviewed articles and 3 books. Prof. Mohanty is the current Chair of Technical Committee on Very Large Scale Integration (TCVLSI) of the IEEE Computer Society, is on the editorial board of IET Circuits, Devices and Systems, Integration and Journal of Low Power Electronics, and serves on the organizing and program committee of several international conferences.Ashok Srivastava is Professor of Engineering at the Division of Electrical & Computer Engineering of Louisiana State University, Baton Rouge, where his research interests lie in low-power VLSI design and testability for nanoscale transistors and integration, and nanoelectronics with focus on novel emerging devices and integrated circuit design based on carbon nanotubes, graphene and other reduced dimension 2D materials. He is the author of more than 160 technical papers including conference proceedings, book chapters, a patent and a book on Carbon Based Electronics. Prof. Srivastava serves on the Editorial Review Board of Modeling and Numerical Simulation of Material Science (MNSMS), Journal of Material Science and Chemical Engineering (JMSCE), The Scientific World Journal (Electronics) and is Editor-in-Chief of the Journal of Sensor Technology.

• Chapter 1: High-κ dielectrics and device reliabilityChapter 2: High mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arraysChapter 3: Anodic metal-insulator-metal (MIM) capacitorsChapter 4: Graphene transistors - present and beyondChapter 5: Junction and doping-free transistors for future computingChapter 6: Nanoscale high-κ/metal-gate CMOS and FinFET based logic librariesChapter 7: FinFET and reliability considerations of next-generation processorsChapter 8: Multiple-independent-gate nanowire transistors: from technology to advanced SoC designChapter 9: Exploration of carbon nanotubes for efficient power deliveryChapter 10: Timing driven buffer insertion for carbon nanotube interconnectsChapter 11: Memristor modeling - static, statistical, and stochastic methodologiesChapter 12: Neuromorphic devices and circuits