Woogeun Rhee is a Professor in the Institute of Microelectronics and the Department of Microelectronics and Nanoelectronics at Tsinghua University, Beijing, China. He has over 20 years of professional career in integrated circuit design with nearly 10 years in industry and 13 years in academia. From 1997 to 2001, he was with Conexant Systems, Newport Beach, CA, where he developed a low-power low-cost fractional-N frequency synthesizer product. From 2001 to 2006, he was with IBM Thomas J. Watson Research Center, Yorktown Heights, NY and worked on clocking circuits for high-speed I/O serial links, including low-jitter phase-locked loops, clock-and-data recovery circuits, and on-chip testability circuits. He has published ›150 IEEE publications and currently holds 24 US patents. He is an IEEE Distinguished Lecturer (2016-2017) and an Ex-Officio Administrative Committee (AdCom) member of the Solid-State Circuits Society (2020).

• Part I: Basic architectures and system perspectivesChapter 1: Evolution of monolithic phase-locked loopsChapter 2: Fractional-N frequency synthesisChapter 3: Clock data recovery: a system perspectiveChapter 4: Silicon-based THz frequency synthesizers with wide locking range Part II: Digital-intensive phase-locked loopsChapter 5: Time-to-digital convertersChapter 6: Bang-bang digital PLLs for wireless systemsChapter 7: Hybrid PLLsChapter 8: Spur mitigation techniques for DPLL architectureChapter 9: Fully synthesized digital PLLChapter 10: Ultra-low-power ADPLL Part III: Low-noise frequency generation and modulationChapter 11: Integrated LC oscillatorsChapter 12: Mm-wave and sub-THz CMOS VCOsChapter 13: Ultra-low phase noise ADPLL for millimeter waveChapter 14: DTC-based subsampling PLLs for low-noise synthesis and two-point modulationChapter 15: Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering Part IV: Clock-and-data recovery and clockingChapter 16: An overview of CDR in ultra-high-speed wireline transceiversChapter 17: Clock and data recovery for optical linksChapter 18: Digital clock and data recovery circuitsChapter 19: Spread spectrum clock generator: a low-cost EMI solutionChapter 20: High-performance CMOS clock distribution Part V: Advanced clock/frequency generationChapter 21: Sub-sampling PLL techniquesChapter 22: PLLs with nested frequency-locked loopChapter 23: Time amplified charge pump PLLChapter 24: Multiplying DLLsChapter 25: Wideband PLLs

Woogeun Rhee is a Professor in the Institute of Microelectronics and the Department of Microelectronics and Nanoelectronics at Tsinghua University, Beijing, China. He has over 20 years of professional career in integrated circuit design with nearly 10 years in industry and 13 years in academia. From 1997 to 2001, he was with Conexant Systems, Newport Beach, CA, where he developed a low-power low-cost fractional-N frequency synthesizer product. From 2001 to 2006, he was with IBM Thomas J. Watson Research Center, Yorktown Heights, NY and worked on clocking circuits for high-speed I/O serial links, including low-jitter phase-locked loops, clock-and-data recovery circuits, and on-chip testability circuits. He has published ›150 IEEE publications and currently holds 24 US patents. He is an IEEE Distinguished Lecturer (2016-2017) and an Ex-Officio Administrative Committee (AdCom) member of the Solid-State Circuits Society (2020).

• Part I: Basic architectures and system perspectivesChapter 1: Evolution of monolithic phase-locked loopsChapter 2: Fractional-N frequency synthesisChapter 3: Clock data recovery: a system perspectiveChapter 4: Silicon-based THz frequency synthesizers with wide locking range Part II: Digital-intensive phase-locked loopsChapter 5: Time-to-digital convertersChapter 6: Bang-bang digital PLLs for wireless systemsChapter 7: Hybrid PLLsChapter 8: Spur mitigation techniques for DPLL architectureChapter 9: Fully synthesized digital PLLChapter 10: Ultra-low-power ADPLL Part III: Low-noise frequency generation and modulationChapter 11: Integrated LC oscillatorsChapter 12: Mm-wave and sub-THz CMOS VCOsChapter 13: Ultra-low phase noise ADPLL for millimeter waveChapter 14: DTC-based subsampling PLLs for low-noise synthesis and two-point modulationChapter 15: Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering Part IV: Clock-and-data recovery and clockingChapter 16: An overview of CDR in ultra-high-speed wireline transceiversChapter 17: Clock and data recovery for optical linksChapter 18: Digital clock and data recovery circuitsChapter 19: Spread spectrum clock generator: a low-cost EMI solutionChapter 20: High-performance CMOS clock distribution Part V: Advanced clock/frequency generationChapter 21: Sub-sampling PLL techniquesChapter 22: PLLs with nested frequency-locked loopChapter 23: Time amplified charge pump PLLChapter 24: Multiplying DLLsChapter 25: Wideband PLLs

Woogeun Rhee is a Professor in the Institute of Microelectronics and the Department of Microelectronics and Nanoelectronics at Tsinghua University, Beijing, China. He has over 20 years of professional career in integrated circuit design with nearly 10 years in industry and 13 years in academia. From 1997 to 2001, he was with Conexant Systems, Newport Beach, CA, where he developed a low-power low-cost fractional-N frequency synthesizer product. From 2001 to 2006, he was with IBM Thomas J. Watson Research Center, Yorktown Heights, NY and worked on clocking circuits for high-speed I/O serial links, including low-jitter phase-locked loops, clock-and-data recovery circuits, and on-chip testability circuits. He has published ›150 IEEE publications and currently holds 24 US patents. He is an IEEE Distinguished Lecturer (2016-2017) and an Ex-Officio Administrative Committee (AdCom) member of the Solid-State Circuits Society (2020).

• Part I: Basic architectures and system perspectivesChapter 1: Evolution of monolithic phase-locked loopsChapter 2: Fractional-N frequency synthesisChapter 3: Clock data recovery: a system perspectiveChapter 4: Silicon-based THz frequency synthesizers with wide locking range Part II: Digital-intensive phase-locked loopsChapter 5: Time-to-digital convertersChapter 6: Bang-bang digital PLLs for wireless systemsChapter 7: Hybrid PLLsChapter 8: Spur mitigation techniques for DPLL architectureChapter 9: Fully synthesized digital PLLChapter 10: Ultra-low-power ADPLL Part III: Low-noise frequency generation and modulationChapter 11: Integrated LC oscillatorsChapter 12: Mm-wave and sub-THz CMOS VCOsChapter 13: Ultra-low phase noise ADPLL for millimeter waveChapter 14: DTC-based subsampling PLLs for low-noise synthesis and two-point modulationChapter 15: Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering Part IV: Clock-and-data recovery and clockingChapter 16: An overview of CDR in ultra-high-speed wireline transceiversChapter 17: Clock and data recovery for optical linksChapter 18: Digital clock and data recovery circuitsChapter 19: Spread spectrum clock generator: a low-cost EMI solutionChapter 20: High-performance CMOS clock distribution Part V: Advanced clock/frequency generationChapter 21: Sub-sampling PLL techniquesChapter 22: PLLs with nested frequency-locked loopChapter 23: Time amplified charge pump PLLChapter 24: Multiplying DLLsChapter 25: Wideband PLLs