Ashok Srivastava – författare

Although existing nanometer CMOS technology is expected to remain dominant for the next decade, new non-classical devices are being developed as the potential replacements of silicon CMOS, in order to meet the ever-present demand for faster, smaller, more efficient integrate circuits.Many new devices are based on novel emerging materials such as one-dimensional carbon nanotubes and two-dimensional graphene, non-graphene two-dimensional materials, and transition metal dichalcogenides. Such devices use on/off operations based on quantum mechanical current transport, and so their design and fabrication require an understanding of the electronic structures of materials and technologies. Moreover, new electronic design automation (EDA) tools and techniques need to be developed based on integrating devices from emerging novel material-based technologies.The aim of this book is to explore the materials and design requirements of these emerging integrated circuit technologies, and to outline their prospective applications. It will be useful for academics and research scientists interested in future directions and developments in design, materials and applications of novel integrated circuit technologies, and for research and development professionals working at the cutting edge of integrated circuit development.

The demand for ever smaller and portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturization. To enable even smaller electronics, various nanodevices including carbon nanotube transistors, graphene transistors, tunnel transistors and memristors (collectively called post-CMOS devices) are emerging that could replace the traditional and ubiquitous silicon transistor. This book explores these nanoelectronics at the device level including modelling and design.Topics covered include high-k dielectrics; high mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays; anodic metal-insulator-metal (MIM) capacitors; graphene transistors; junction and doping free transistors; nanoscale gigh-k/metal-gate CMOS and FinFET based logic libraries; multiple-independent-gate nanowire transistors; carbon nanotubes for efficient power delivery; timing driven buffer insertion for carbon nanotube interconnects; memristor modeling; and neuromorphic devices and circuits.This book is essential reading for researchers, research-focused industry designers/developers, and advanced students working on next-generation electronic devices and circuits.

The demand for ever smaller and portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturization. To enable even smaller electronics, various nanodevices including carbon nanotube transistors, graphene transistors, tunnel transistors and memristors (collectively called post-CMOS devices) are emerging that could replace the traditional and ubiquitous silicon transistor. This book explores these nanoelectronics at the circuit and systems levels including modelling and design approaches and issues.Topics covered include self-healing analog and radio frequency circuits; on-chip gate delay variability measurement in scaled technology node; nanoscale finFET devices for PVT aware SRAM; data stability and write ability enhancement techniques for finFET SRAM circuits; low-leakage techniques for nanoscale CMOS circuits; thermal effects in carbon nanotube VLSI interconnects; lumped electro-thermal modeling and analysis of carbon nanotube interconnects; high-level synthesis of digital integrated circuits in the nanoscale mobile electronics era; SPICEless RTL design optimization of nanoelectronic digital integrated circuits; green on-chip inductors for three-dimensional integrated circuits; 3D network-on-chips; and DNA computing.This book is essential reading for researchers, research-focused industry designers/developers, and advanced students working on next-generation electronic devices and circuits.

Discovery of one-dimensional material carbon nanotubes in 1991 by the Japanese physicist Dr. Sumio Iijima has resulted in voluminous research in the field of carbon nanotubes for numerous applications, including possible replacement of silicon used in the fabrication of CMOS chips. One interesting feature of carbon nanotubes is that these can be metallic or semiconducting with a bandgap depending on their diameter. In search of non-classical devices and related technologies, both carbon nanotube-based field-effect transistors and metallic carbon nanotube interconnects are being explored extensively for emerging logic devices and very large-scale integration. Although various models for carbon nanotube-based transistors and interconnects have been proposed in the literature, an integrated approach to make them compatible with the present simulators is yet to be achieved. This book makes an attempt in this direction for the carbon-based electronics through fundamentals of solid-state physics and devices.