Advanced ASIC Chip Synthesis

This volume describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is examined. The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. It includes a design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described. In addition, issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed. This book also contains discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.