Structured Computer Organization

International Edition

AvAndrew Tanenbaum,Todd Austin

Häftad, Engelska, 2012

1 212 kr

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Beskrivning

Structured Computer Organization, specifically written for undergraduate students, is a best-selling guide that provides an accessible introduction to computer hardware and architecture. This text will also serve as a useful resource for all computer professionals and engineers who need an overview or introduction to computer architecture. This book takes a modern structured, layered approach to understanding computer systems. It's highly accessible - and it's been thoroughly updated to reflect today's most critical new technologies and the latest developments in computer organization and architecture. Tanenbaum’s renowned writing style and painstaking research make this one of the most accessible and accurate books available, maintaining the author’s popular method of presenting a computer as a series of layers, each one built upon the ones below it, and understandable as a separate entity.

Produktinformation

Utgivningsdatum:2012-10-19
Mått:180 x 232 x 32 mm
Vikt:1 044 g
Format:Häftad
Språk:Engelska
Antal sidor:800
Upplaga:6
Förlag:Pearson Education
ISBN:9780273769248

Utforska kategorier

Systemvetenskap och AI inom Data och IT

Innehållsförteckning

CHAPTER 1 INTRODUCTION1.1 STRUCTURED COMPUTER ORGANIZATION1.1.1 Languages, Levels, and Virtual Machines1.1.2 Contemporary Multilevel Machines1.1.3 Evolution of Multilevel Machines1.2 MILESTONES IN COMPUTER ARCHITECTURE1.2.1 The Zeroth Generation (Mechanical Computers (1642-1945))1.2.2 The First Generation (Vacuum Tubes (1945-1955))1.2.3 The Second Generation (Transistors (1955-1965))1.2.4 The Third Generation (Integrated Circuits (1965-1980))1.2.5 The Fourth Generation (Very Large Scale Integration (1980-?))1.2.6 The Fifth Generation (Low-Power and Invisible Computers)1.3 THE COMPUTER ZOO1.3.1 Technological and Economic Forces1.3.2 The Computer Spectrum1.3.3 Disposable Computers1.3.4 Microcontrollers1.3.5 Mobile and Game Computers1.3.6 Personal Computers1.3.7 Servers1.3.8 Mainframes1.4 EXAMPLE COMPUTER FAMILIES1.4.1 Introduction to the x86 Architecture1.4.2 Introduction to the ARM Architecture1.4.3 Introduction to the AVR Architecture1.5 METRIC UNITS1.6 OUTLINE OF THIS BOOKCHAPTER 2 COMPUTER SYSTEMS ORGANIZATION2.1 PROCESSORS2.1.1 CPU Organization2.1.2 Instruction Execution2.1.3 RISC versus CISC2.1.4 Design Principles for Modern Computers2.1.5 Instruction-Level Parallelism2.1.6 Processor-Level Parallelism2.2 PRIMARY MEMORY2.2.1 Bits2.2.2 Memory Addresses2.2.3 Byte Ordering2.2.4 Error-Correcting Codes2.2.5 Cache Memory2.2.6 Memory Packaging and Types2.3 SECONDARY MEMORY2.3.1 Memory Hierarchies2.3.2 Magnetic Disks2.3.3 IDE Disks2.3.4 SCSI Disks2.3.5 RAID2.3.6 Solid-State Disks2.3.7 CD-ROMs2.3.8 CD-Recordables2.3.9 CD-Rewritables2.3.10 DVD2.3.11 Blu-ray2.4 INPUT/OUTPUT2.4.1 Buses2.4.2 Terminals2.4.3 Mice2.4.4 Game Controllers2.4.5 Printers2.4.6 Telecommunications Equipment2.4.7 Digital Cameras2.4.8 Character Codes2.5 SUMMARYCHAPTER 3 THE DIGITAL LOGIC LEVEL3.1 GATES AND BOOLEAN ALGEBRA3.1.1 Gates3.1.2 Boolean Algebra3.1.3 Implementation of Boolean Functions3.1.4 Circuit Equivalence3.2 BASIC DIGITAL LOGIC CIRCUITS3.2.1 Integrated Circuits3.2.2 Combinational Circuits3.2.3 Arithmetic Circuits3.2.4 Clocks3.3 MEMORY3.3.1 Latches3.3.2 Flip-Flops3.3.3 Registers3.3.4 Memory Organization3.3.5 Memory Chips3.3.6 RAMs and ROMs3.4 CPU CHIPS AND BUSES3.4.1 CPU Chips3.4.2 Computer Buses3.4.3 Bus Width3.4.4 Bus Clocking3.4.5 Bus Arbitration3.4.6 Bus Operations3.5 EXAMPLE CPU CHIPS3.5.1 The Intel Core i73.5.2 The Texas Instruments OMAP4430 System-on-a-Chip3.5.3 The Atmel ATmega168 Microcontroller3.6 EXAMPLE BUSES3.6.1 The PCI Bus3.6.2 PCI Express3.6.3 The Universal Serial Bus3.7 INTERFACING3.7.1 I/O Interfaces3.7.2 Address Decoding3.8 SUMMARYCHAPTER 4 THE MICROARCHITECTURE LEVEL4.1 AN EXAMPLE MICROARCHITECTURE4.1.1 The Data Path4.1.2 Microinstructions4.1.3 Microinstruction Control: The Mic-14.2 AN EXAMPLE ISA: IJVM4.2.1 Stacks4.2.2 The IJVM Memory Model4.2.3 The IJVM Instruction Set4.2.4 Compiling Java to IJVM4.3 AN EXAMPLE IMPLEMENTATION4.3.1 Microinstructions and Notation4.3.2 Implementation of IJVM Using the Mic-14.4 DESIGN OF THE MICROARCHITECTURE LEVEL4.4.1 Speed versus Cost4.4.2 Reducing the Execution Path Length4.4.3 A Design with Prefetching: The Mic-24.4.4 A Pipelined Design: The Mic-34.4.5 A Seven-Stage Pipeline: The Mic-44.5 IMPROVING PERFORMANCE4.5.1 Cache Memory4.5.2 Branch Prediction4.5.3 Out-of-Order Execution and Register Renaming4.5.4 Speculative Execution4.6 EXAMPLES OF