Bokus
Erik Seligman, M .V. Achutha Kiran Kumar, Anshul Jain - Formal Verification Testbenches, Häftad

Häftad, Engelska, 2027

Formal Verification Testbenches

Using Patterns for Reusable and Repeatable VLSI Design Quality

Av Erik Seligman, M .V. Achutha Kiran Kumar, Anshul Jain

1556 kr

Kommande

Beskrivning
Formal Verification (FV) has become an essential technology in the verification of IP, core, or SOC design. The authors' previous book, “Formal Verification: An Essential Toolkit for Modern VLSI Design”, offered the definitive guide to design and validation, with advice to help working engineers integrate these techniques into their work. However, understanding the technology is only the beginning: to really use FV effectively, there are many practical considerations in creating effective testbenches. It’s important to use the right formal tools depending on the preferred design style, project phase, and verification goals. Formal Verification Testbenches: Using Patterns for Reusable and Repeatable VLSI Design Quality is designed to provide that guidance, to assist the transition from initial FV usage to FV being the main workhorse of the validation flow. In addition to describing general principles of FV testbench development that apply to any design style, the book takes a deep dive into real testbenches for specific examples: arbiters, sequence controllers, memory controllers, fsm-heavy control blocks, clock gating designs, and dot-product accumulate blocks. It also highlights new opportunities within the field, for example using AI to plan and execute FV. Formal Verification Testbenches: Using Patterns for Reusable and Repeatable VLSI Design Quality enables a design team to confidently plan and execute a project whose primary validation method will be formal verification.

  • Explains how to write workable formal verification testbenches
  • Considers areas within which formal verification is an option
  • Discusses techniques for abstracting formal verification problems to make them more tractable
  • Teaches the concepts of Architecture formal, compliance Monitor, Arbitration and FPV tools
  • Offers practical Testbenches: arbiters, sequence controllers, inter-related FSMs, memory controller, clock gating, CvsRTL on dot product accumulate design, post silicon bug reproduction
  • Examines best practices and pitfalls within FV, and considers the future of the field
  • Includes a supplementary website containing downloadable code samples.
Produktinformation
  • Utgivningsdatum: 2027-07-01
  • Mått: 191 x 235 x undefined mm
  • Vikt: 450 g
  • Format: Häftad
  • Språk: Engelska
  • Antal sidor: 500
  • Förlag: Elsevier Science
  • ISBN: 9780443428890
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Mer om författaren

Erik Seligman is currently a Senior Product Engineering Architect at Cadence Design Systems, where he helps to plan and support the Jasper Formal Verification tool suite. Previously he worked at Intel Corporation in Hillsboro, Oregon for over two decades, in a variety of positions involving software, design, simulation, and formal verification. In his spare time he hosts the “Math Mutation” podcast, and has served as an elected director on the Hillsboro school board. M V Achutha Kiran Kumar is an Intel Fellow in the Design Engineering group at intel and leads the company’s Formal Verification Central Technology Office, one of the largest industrial Formal Verification teams in the world. He has over 19 years experience where he worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation and various levels of validation including formal verification. He is the co-author of 'Formal Verification - An Essential toolkit for the Hardware Design'. Anshul Jain is the Principal Engineer at Intel’s Formal Verification Central Technology Office, and formerly a Formal Verification consultant at Oski Technologies.

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