Advanced FPGA Design

Steve Kilts is a cofounder and principal engineer at Spectrum Design Solutions, an engineering consulting firm based out of Minneapolis, Minnesota (www.spectrumdsi.com). Mr. Kilts and his team at Spectrum have successfully completed projects for clients ranging from Fortune 100 companies to small start-ups. His FPGA design experience is extensive and includes applications in audio, DSP, high-speed computing and bus architectures, IC testers, industrial automation and control, embedded microprocessors, PCI, medical system design, commercial aviation, and ASIC prototyping. Mr. Kilts has many years of experience making performance trade-offs for FPGA designs targeting high speed, area reduction, and low power. He holds a master of science degree in electrical engineering from the University of Minnesota.

"Advanced FPGA Design is an excellent and concise reference book that is suitable for engineers already familiar with the fundamentals of FPGA design. (IEEE Signal Processing Magazine, November 2008)

• Preface xiiiAcknowledgments xv1. Architecting Speed 11.1 High Throughput 21.2 Low Latency 41.3 Timing 61.3.1 Add Register Layers 61.3.2 Parallel Structures 81.3.3 Flatten Logic Structures 101.3.4 Register Balancing 121.3.5 Reorder Paths 141.4 Summary of Key Points 162. Architecting Area 172.1 Rolling Up the Pipeline 182.2 Control-Based Logic Reuse 202.3 Resource Sharing 232.4 Impact of Reset on Area 252.4.1 Resources Without Reset 252.4.2 Resources Without Set 262.4.3 Resources Without Asynchronous Reset 272.4.4 Resetting RAM 292.4.5 Utilizing Set/Reset Flip-Flop Pins 312.5 Summary of Key Points 343. Architecting Power 373.1 Clock Control 383.1.1 Clock Skew 393.1.2 Managing Skew 403.2 Input Control 423.3 Reducing the Voltage Supply 443.4 Dual-Edge Triggered Flip-Flops 443.5 Modifying Terminations 453.6 Summary of Key Points 464. Example Design: The Advanced Encryption Standard 474.1 AES Architectures 474.1.1 One Stage for Sub-bytes 514.1.2 Zero Stages for Shift Rows 514.1.3 Two Pipeline Stages for Mix-Column 524.1.4 One Stage for Add Round Key 524.1.5 Compact Architecture 534.1.6 Partially Pipelined Architecture 574.1.7 Fully Pipelined Architecture 604.2 Performance Versus Area 664.3 Other Optimizations 675. High-Level Design 695.1 Abstract Design Techniques 695.2 Graphical State Machines 705.3 DSP Design 755.4 Software/Hardware Codesign 805.5 Summary of Key Points 816. Clock Domains 836.1 Crossing Clock Domains 846.1.1 Metastability 866.1.2 Solution 1: Phase Control 886.1.3 Solution 2: Double Flopping 896.1.4 Solution 3: FIFO Structure 926.1.5 Partitioning Synchronizer Blocks 976.2 Gated Clocks in ASIC Prototypes 976.2.1 Clocks Module 986.2.2 Gating Removal 996.3 Summary of Key Points 1007. Example Design: I2S Versus SPDIF 1017.1 I2S 1017.1.1 Protocol 1027.1.2 Hardware Architecture 1027.1.3 Analysis 1057.2 SPDIF 1077.2.1 Protocol 1077.2.2 Hardware Architecture 1087.2.3 Analysis 1148. Implementing Math Functions 1178.1 Hardware Division 1178.1.1 Multiply and Shift 1188.1.2 Iterative Division 1198.1.3 The Goldschmidt Method 1208.2 Taylor and Maclaurin Series Expansion 1228.3 The CORDIC Algorithm 1248.4 Summary of Key Points 1269. Example Design: Floating-Point Unit 1279.1 Floating-Point Formats 1279.2 Pipelined Architecture 1289.2.1 Verilog Implementation 1319.2.2 Resources and Performance 13710. Reset Circuits 13910.1 Asynchronous Versus Synchronous 14010.1.1 Problems with Fully Asynchronous Resets 14010.1.2 Fully Synchronized Resets 14210.1.3 Asynchronous Assertion, Synchronous Deassertion 14410.2 Mixing Reset Types 14510.2.1 Nonresetable Flip-Flops 14510.2.2 Internally Generated Resets 14610.3 Multiple Clock Domains 14810.4 Summary of Key Points 14911. Advanced Simulation 15111.1 Testbench Architecture 15211.1.1 Testbench Components 15211.1.2 Testbench Flow 15311.1.2.1 Main Thread 15311.1.2.2 Clocks and Resets 15411.1.2.3 Test Cases 15511.2 System Stimulus 15711.2.1 MATLAB 15711.2.2 Bus-Functional Models 15811.3 Code Coverage 15911.4 Gate-Level Simulations 15911.5 Toggle Coverage 16211.6 Run-Time Traps 16511.6.1 Timescale 16511.6.2 Glitch Rejection 16511.6.3 Combinatorial Delay Modeling 16611.7 Summary of Key Points 16912. Coding for Synthesis 17112.1 Decision Trees 17212.1.1 Priority Versus Parallel 17212.1.2 Full Conditions 17612.1.3 Multiple Control Branches 17912.2 Traps 18012.2.1 Blocking Versus Nonblocking 18012.2.2 For-Loops 18312.2.3 Combinatorial Loops 18512.2.4 Inferred Latches 18712.3 Design Organization 18812.3.1 Partitioning 18812.3.1.1 Data Path Versus Control 18812.3.1.2 Clock and Reset Structures 18912.3.1.3 Multiple Instantiations 19012.3.2 Parameterization 19112.3.2.1 Definitions 19112.3.2.2 Parameters 19212.3.2.3 Parameters in Verilog-2001 19412.4 Summary of Key Points 19513. Example Design: The Secure Hash Algorithm 19713.1 SHA-1 Architecture 19713.2 Implementation Results 20414. Synthesis Optimization 20514.1 Speed Versus Area 20614.2 Resource Sharing 20814.3 Pipelining, Retiming, and Register Balancing 21114.3.1 The Effect of Reset on Register Balancing 21314.3.2 Resynchronization Registers 21514.4 FSM Compilation 21614.4.1 Removal of Unreachable States 21914.5 Black Boxes 22014.6 Physical Synthesis 22314.6.1 Forward Annotation Versus Back-Annotation 22414.6.2 Graph-Based Physical Synthesis 22514.7 Summary of Key Points 22615. Floorplanning 22915.1 Design Partitioning 22915.2 Critical-Path Floorplanning 23215.3 Floorplanning Dangers 23315.4 Optimal Floorplanning 23415.4.1 Data Path 23415.4.2 High Fan-Out 23415.4.3 Device Structure 23515.4.4 Reusability 23815.5 Reducing Power Dissipation 23815.6 Summary of Key Points 24016. Place and Route Optimization 24116.1 Optimal Constraints 24116.2 Relationship between Placement and Routing 24416.3 Logic Replication 24616.4 Optimization across Hierarchy 24716.5 I/O Registers 24816.6 Pack Factor 25016.7 Mapping Logic into RAM 25116.8 Register Ordering 25116.9 Placement Seed 25216.10 Guided Place and Route 25416.11 Summary of Key Points 25417. Example Design: Microprocessor 25717.1 SRC Architecture 25717.2 Synthesis Optimizations 25917.2.1 Speed Versus Area 26017.2.2 Pipelining 26117.2.3 Physical Synthesis 26217.3 Floorplan Optimizations 26217.3.1 Partitioned Floorplan 26317.3.2 Critical-Path Floorplan: Abstraction 1 26417.3.3 Critical-Path Floorplan: Abstraction 2 26518. Static Timing Analysis 26918.1 Standard Analysis 26918.2 Latches 27318.3 Asynchronous Circuits 27618.3.1 Combinatorial Feedback 27718.4 Summary of Key Points 27819. PCB Issues 27919.1 Power Supply 27919.1.1 Supply Requirements 27919.1.2 Regulation 28319.2 Decoupling Capacitors 28319.2.1 Concept 28319.2.2 Calculating Values 28519.2.3 Capacitor Placement 28619.3 Summary of Key Points 288Appendix A 289Appendix B 303Bibliography 319Index 321