Peter D. Minns, Northumbria University, School of Computing, Engineering, and Information Sciences, Newcastle Upon TyneDr Peter Minns has been at Northumbria University since 1984, now holding the position of Senior Lecturer in the School of Computing, Engineering and Information Sciences. He teaches courses on electrical circuit theory, electronics, programming and embedded system design to both undergraduates and post graduates, and is also involved in teaching company schemes in industry. Previous to this, he has worked for many years as a practising engineer specializing in both the telecommunications and embedded microprocessor fields. His current research interest is in the development of finite state machines (FSMs). Ian David Elliott, Northumbria University, School of Computing, Engineering, and Information Sciences, Newcastle Upon TyneIan Elliott has been a lecturer in further and higher education for over 20 years, currently holding the position of Senior Lecturer in the School of Computing, Engineering and Information Sciences, at Northumbria University. He has taught a wide range of subjects in the field of electronics, as well as working as a consultant in industry, carrying out research into integrated circuit testing. He now specializes in hardware description languages, specifically Verilog-HDL and Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). He was one of the first academics to introduce the topic of hardware description languages into the curriculum.

• CHAPTER 1 - THE BASICS IntroductionWhat is a Finite State MachineNumber of StatesNumber required for State Diagram - Frame 1.3Mealy FSMMoore FSMClass C FSMIntroduction to the State Diagram – States, Transitions & InputsInput Signals - Frames 1.8 to 1.9,Output Signals - Frame 1.9Inputs and Outputs of FSMInverted Inputs - Frame 1.11Active High Signals - Frames 1.11Assignment - Frame 1.11Non-Unit Distance Coding - Frame 1.11Secondary State VariablesUnit Distance Coding - Frame 1.12 to Frame 1.14.Active Low Signals - Frame 1.14Mealy Outputs - Frame 1.16, 1.19, 1.20, 1.21, fromEffect of clock on Mealy output signalsSummary - Frame 1.22CHAPTER 2 - CONTROLLING OUTSIDE WORLD DEVICESIntroductionUsing Timer to Introduce Wait States - Frame 2.1 to 2.3Analogue to Digital Converters - Frame 2.4Data Acquisition System - Frame 2.4, Frame 2.9 & Frame 2.10 fromMemory:How to Control in FSM’s - Frame 2.5 to 2.10Chip Select & Read and Write SequencesFrames 2.5 to 2.7 - (See also Chapter 4, Section 4.4,Chapter 5, Sections 5.2, 5.3, 5.4, 5.6, 5.8.)Monitoring Inputs for Changes - Frame 2.11 to 2.14Dealing with Incorrect Input States - Frame 2.14SummaryCHAPTER 3 - SYNTHESISING FSMSIntroductionSynthesising using T Type Flip Flops - Frame 3.1 to 3.7T Type Flip FlopT Flip Flop Example in a State DiagramDeveloping T Flip Flop Equations from the State DiagramExamples of Developing T Equations from a Number of State DiagramsSolutions to the ExamplesD Type Flip FlopsDeveloping D Flip Flop Equations from a State DiagramRule 1: Dealing with 1 to 0 with Input TermsRule 2: Dealing with 1 to 1 TransitionsRule 3: Dealing with two-way BranchesUsing the Two-way Branch RuleExamples of Obtaining D Flip Flop Equations from a State DiagramState Diagram with Two-way Branch States: Obtaining D Type EquationsResetting the Flip FlopExamples of Developing D Equations from a Number of State DiagramsSolutions to the ExamplesAsynchronous and Synchronous Resetting of Flip FlopsComplete Design of Circuit for a Particular DesignDealing with Multi-way Branch States using D Type Flip FlopsDealing with Active Low Output Signals in an FSMDealing with Active Low Mealy Output Signals in an FSMSummaryCHAPTER 4 - SYNCHRONOUS FSM DESIGNS4.1 Traditional FSM Design Method Verses Method used in this Book4.2 Dealing with Unused States4.3 High/Low Alarm Indicator System4.4 Simple Waveform Generator4.5 Dice Game4.6 Binary Data Serial Transmitter4.7 Development of a Serial Asynchronous Receiver4.8 Adding Parity Detection to the Serial Receiver System4.9 Asynchronous Serial Transmitter System4.10 Clocked Watchdog Timer4.11 SummaryCHAPTER 5 -ONE HOT DESIGNS5.1 One Hot Technique of FSM Design5.2 Data Acquisition System (DAS)5.3 A Shared Memory System5.4 Fast Waveform Synthesiser5.5 Controlling the FSM from a Microprocessor5.6 Memory Chip Tester5.7 Comparing One Hot Solution with more Conventional DesignMethod of Chapter 45.8 Dynamic Memory Access (DMA) Controller5.9 How to Control the DMA Controller from a Microprocessor5.10 Detecting Binary Sequences using an FSM5.11 SummaryCHAPTER 6 - INTRODUCTION TO VERILOG-HDL A Brief Background to HDLsHardware Modelling with Verilog-HDL - the ModuleModules within Modules : Creating HierarchyVerilog-HDL Simulation : A Complete ExampleReferences and Further ReadingCHAPTER 7 - ELEMENTS OF VERILOG-HDL Built-in Primitives and Types7.1.1 Verilog Types7.1.2 Verilog Logic and Numeric Values7.1.3 Specifying Values7.1.4 Verilog-HDL Primitive GatesOperators and ExpressionsExample Illustrating the use of Verilog-HDL Operators -Hamming Code EncoderReferences and Further ReadingCHAPTER 8 - DESCRIBING COMBINATIONAL AND SEQUENTIAL LOGIC USING VERILOG=HDL The Data Flow Style of Description - Review of theContinuous AssignmentThe Behavioural Style of Description - The Sequential BlockAssignments within Sequential Blocks : Blocking andNon-BlockingDescribing Combinational Logic using a Sequential BlockDescribing Sequential Logic using a Sequential BlockDescribing MemoriesDescribing Finite State Machines:Example 1 Chess Clock Controller FSMExample 2 Combinational Lock FSM with AutomaticLock FeatureReferences and Further ReadingCHAPTER 9 - ASYNCHRONOUS FSM DESIGN9.1 Introduction9.2 Development of Event Driven Logic9.3 Using the Sequential Equations to Synthesise an Event FSM9.3.1 Short Cut Rule9.4 Implementing the Design using Sum of Product as PLD9.5 Development of an Event Version of the Single Pulse Generatorwith Memory FSM9.6 Another event FSM design through to simulation9.7 The Hover Mower FSM9.8 An Example with a Transition Without any Input9.9 Unusual Example responding to a MicroprocessorAddress Location9.10 Example that uses a Mealy Output9.11 Example using a Relay Circuit9.12 Race Conditions in Event FSMs9.13 Wait State Generator for a Microprocessor System9.14 Development of an Asynchronous FSM to Control a ClothesSpin System9.15 SummaryCHAPTER 10 - PETRI-NETS10.1 Introduction to Simple Petri-Nets10.2 Sequential Petri-Net Example, the Pump Spin Motor Problem10.3 Parallel Petri-Nets10.4 Synchronising Flow in a Parallel Petri-Net10.5 Using Enabling/Disabling Arcs to Synchronise Flow betweenTwo Petri-Nets10.6 Example - Control of Shared Resource10.7 A Serial Receiver of Binary Data using a Petri-Net Controller10.8 SummaryAPPENDIX INDEXAPPENDIX A1 - LOGIC GATES AND BOOLEAN ALGEBRA IN THE BOOKIntroductionA1.1 Basic Gate Symbols used in the BookA1.2 Exclusive OR and Exclusive NOR SymbolsA1.3 Laws of Boolean Algebra:A1.3.1 Basic OR RulesA1.3.2 Basic AND RulesA1.3.3 Associative Laws and Commutative LawsA1.3.4 Distributive LawsA1.3.5 Auxiliary Law - For Static 1 Hazard RemovalA1.3.5.1 Proof of the Auxiliary LawA1.3.6 The Consensus TheoremA1.3.7 Effect of Signal Delay on Logic GatesA1.3.8 De-Morgans TheoremA1.4 Examples of Applying the Laws of Boolean AlgebraA1.4.1 Converting AND-OR to NANDA1.4.2 Converting AND-OR to NORA1.4.3 Logical Adjacency RuleA1.5 SummaryAPPENDIX A2 - COUNTING & SHIFTING CIRCUIT TECHNIQUESIntroductionA2.1 Basic Up Down Synchronous Binary Counter DevelopmentA2.2 Example of a Four Bit Synchronous up Counter using T Flip FlopsA2.3 Parallel Loading CountersA2.4 Using D Flip Flops to Build Parallel Loading CountersA2.5 Simple Binary Up CounterA2.6 Clock Circuit to Drive the Counter (and FSMs)A2.7 Counter Design using Don’t CaresA2.8 Shift RegistersA2.9 Asynchronous Receiver Details for Section 4.7 Chapter 4A2.9.1 Eleven Bit Shift Register for the AsynchronousReceiver ModuleA2.9.2 Divide by Eleven CounterA2.9.3 Complete Simulation of the AsynchronousReceiver SystemA2.10 SummaryAPPENDIX A3 - TUTORIAL ON THE USE OF VERILOG HDLTO SIMULATE AN FSM DESIGNA3.1 IntroductionA3.2 Single Pulse with Memory Synchronous FSM DesignA3.2.1 SpecificationA3.2.2 Block DiagramA3.2.3 State DiagramA3.2.4 Equations from the State DiagramA3.2.5 Translation into a Verilog DescriptionA3.3 Test Bench Module and its PurposeA3.4 Using the Verilogger SimulatorA3.4.1 Output from the SimulatorA3.5 SummaryAPPENDIX A4 - IMPLEMENTING STATE MACHINES USING VERILOG BEHAVIOURAL MODEA4.1 IntroductionA4.2 Example 1- The Single Pulse with Memory FSM RevisitedA4.3 The Memory Tester in Chapter 5, Section 5.6 RevisitedA4.4 Summary