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    1. Naturvetenskap och teknik
    2. Teknik och industri
    3. Elektronik och kommunikationer

    All-Digital Frequency Synthesizer in Deep-Submicron CMOS

    AvRobert Bogdan Staszewski,Poras T. Balsara

    Inbunden, Engelska, 2006

    1 902 kr

    Beställningsvara. Skickas inom 5-8 vardagar. Fri frakt över 249 kr.

    Beskrivning

    A new and innovative paradigm for RF frequency synthesis and wireless transmitter design Learn the techniques for designing and implementing an all-digital RF frequency synthesizer. In contrast to traditional RF techniques, this innovative book sets forth digitally intensive design techniques that lead the way to the development of low-cost, low-power, and highly integrated circuits for RF functions in deep submicron CMOS processes. Furthermore, the authors demonstrate how the architecture enables readers to integrate an RF front-end with the digital back-end onto a single silicon die using standard ASIC design flow.Taking a bottom-up approach that progressively builds skills and knowledge, the book begins with an introduction to basic concepts of frequency synthesis and then guides the reader through an all-digital RF frequency synthesizer design: Chapter 2 presents a digitally controlled oscillator (DCO), which is the foundation of a novel architecture, and introduces a time-domain model used for analysis and VHDL simulationChapter 3 adds a hierarchical layer of arithmetic abstraction to the DCO that makes it easier to operate algorithmicallyChapter 4 builds a phase correction mechanism around the DCO such that the system's frequency drift or wander performance matches that of the stable external frequency referenceChapter 5 presents an application of the all-digital RF synthesizerChapter 6 describes the behavioral modeling and simulation methodology used in designThe final chapter presents the implementation of a full transmitter and experimental results. The novel ideas presented here have been implemented and proven in two high-volume, commercial single-chip radios developed at Texas Instruments: Bluetooth and GSM.While the focus of the book is on RF frequency synthesizer design, the techniques can be applied to the design of other digitally assisted analog circuits as well. This book is a must-read for students and engineers who want to learn a new paradigm for RF frequency synthesis and wireless transmitter design using digitally intensive design techniques.

    Produktinformation

    • Utgivningsdatum:2006-09-22
    • Mått:163 x 236 x 25 mm
    • Vikt:583 g
    • Format:Inbunden
    • Språk:Engelska
    • Antal sidor:280
    • Förlag:John Wiley & Sons Inc
    • ISBN:9780471772552

    Utforska kategorier

    • Elektronik och kommunikationer inom Naturvetenskap och teknik

    Mer om författaren

    ROBERT BOGDAN STASZEWSKI, PhD, is a Distinguished Member of Technical Staff with the Digital RF Processor Group of Texas Instruments, where he co-invented and developed the Digital RF Processor (DRPTM), a novel, all-digital transmitter and digitally intensive direct-sampling receiver architecture. Before joining Texas Instruments, Dr. Staszewski worked with Alcatel Network Systems as a design engineer. PORAS T. BALSARA, PhD, is Professor of Electrical Engineering at the Erik Jonsson School of Engineering and Computer Science, The University of Texas at Dallas, where he teaches and conducts research in high-speed, low-power circuit design, VLSI circuits and architectures for signal processing and communication, and reconfigurable systems. He is also the Director of the University's Center for Integrated Circuits and Systems.

    Innehållsförteckning

    • PREFACE xiii1 INTRODUCTION 11.1 Frequency Synthesis 11.1.1 Noise in Oscillators 21.1.2 Frequency Synthesis Techniques 51.2 Frequency Synthesizer as an Integral Part of an RF Transceiver 91.2.1 Transmitter 101.2.2 Receiver 111.2.3 Toward Direct Transmitter Modulation 121.3 Frequency Synthesizers for Mobile Communications 161.3.1 Integer-N PLL Architecture 171.3.2 Fractional-N PLL Architecture 181.3.3 Toward an All-Digital PLL Approach 231.4 Implementation of an RF Synthesizer 251.4.1 CMOS vs. Traditional RF Process Technologies 251.4.2 Deep-Submicron CMOS 251.4.3 Digitally Intensive Approach 261.4.4 System Integration 271.4.5 System Integration Challenges for Deep-Submicron CMOS 292 DIGITALLY CONTROLLED OSCILLATOR 302.1 Varactor in a Deep-Submicron CMOS Process 312.2 Fully Digital Control of Oscillating Frequency 332.3 LC Tank 352.4 Oscillator Core 372.5 Open-Loop Narrowband Digital-to-Frequency Conversion 392.6 Example Implementation 452.7 Time-Domain Mathematical Model of a DCO 472.8 Summary 513 NORMALIZED DCO 523.1 Oscillator Transfer Function and Gain 523.2 DCO Gain Estimation 533.3 DCO Gain Normalization 543.4 Principle of Synchronously Optimal DCO Tuning Word Retiming 553.5 Time Dithering of DCO Tuning Input 563.5.1 Oscillator Tune Time Dithering Principle 563.5.2 Direct Time Dithering of Tuning Input 573.5.3 Update Clock Dithering Scheme 593.6 Implementation of PVT and Acquisition DCO Bits 603.7 Implementation of Tracking DCO Bits 643.7.1 High-Speed Dithering of Fractional Varactors 643.7.2 Dynamic Element Matching of Varactors 703.7.3 DCO Varactor Rearrangement 713.8 Time-Domain Model 733.9 Summary 744 ALL-DIGITAL PHASE-LOCKED LOOP 764.1 Phase-Domain Operation 774.2 Reference Clock Retiming 794.3 Phase Detection 814.3.1 Difference Mode of ADPLL Operation 854.3.2 Integer-Domain Operation 864.4 Modulo Arithmetic of the Reference and Variable Phases 864.4.1 Variable-Phase Accumulator (PV Block) 894.5 Time-to-Digital Converter 914.5.1 Frequency Reference Edge Estimation 934.6 Fractional Error Estimator 944.6.1 Fractional-Division Ratio Compensation 964.6.2 TDC Resolution Effect on Estimated Frequency Resolution 974.6.3 Active Removal of Fractional Spurs Through TDC (Optional) 984.7 Frequency Reference Retiming by a DCO Clock 1004.7.1 Sense Amplifier–Based Flip-Flop 1024.7.2 General Idea of Clock Retiming 1034.7.3 Implementation 1044.7.4 Time-Deferred Calculation of the Variable Phase (Optional) 1074.8 Loop Gain Factor 1094.8.1 Phase-Error Dynamic Range 1114.9 Phase-Domain ADPLL Architecture 1124.9.1 Close-in Spurs Due to Injection Pulling 1144.10 PLL Frequency Response 1154.10.1 Conversion Between the s- and z-Domains 1194.11 Noise and Error Sources 1194.11.1 TDC Resolution Effect on Phase Noise 1204.11.2 Phase Noise Due to DCO SD Dithering 1224.12 Type II ADPLL 1274.12.1 PLL Frequency Response of a Type II Loop 1304.13 Higher-Order ADPLL 1334.13.1 PLL Stability Analysis 1364.14 Nonlinear Differential Term of an ADPLL 1394.14.1 Quality Monitoring of an RF Clock 1404.15 DCO Gain Estimation Using a PLL 1414.16 Gear Shifting of PLL Gain 1424.16.1 Autonomous Gear-Shifting Mechanism 1434.16.2 Extended Gear-Shifting Scheme with Zero-Phase Restart 1484.17 Edge Skipping Dithering Scheme (Optional) 1544.18 Summary 1555 APPLICATION: ADPLL-BASED TRANSMITTER 1565.1 Direct Frequency Modulation of a DCO 1575.1.1 Discrete-Time Frequency Modulation 1585.1.2 Hybrid of Predictive/Closed PLL Operation 1585.1.3 Effect of FREF/CKR Clock Misalignment 1635.2 Just-in-Time DCO Gain Calculation 1645.3 GFSK Pulse Shaping of Transmitter Data 1675.3.1 Interpolative Filter Operation 1725.4 Power Amplifier 1755.5 Digital Amplitude Modulation 1775.5.1 Discrete Pulse-Slimming Control 1805.5.2 Regulation of Transmitting Power 1815.5.3 Tuning Word Adjustment 1825.5.4 Fully Digital Amplitude Control 1835.6 Going Forward: Polar Transmitter 1835.6.1 Generic Modulator 1865.6.2 Polar TX Realization 1875.7 Summary 1886 BEHAVIORAL MODELING AND SIMULATION 1896.1 Simulation Methodology 1906.2 Digital Blocks 1916.3 Support of Digital Stream Processing 1926.4 Random Number Generator 1926.5 Time-Domain Modeling of DCO Phase Noise 1926.5.1 Modeling Oscillator Jitter 1926.5.2 Modeling Oscillator Wander 1946.5.3 Modeling Oscillator Flicker (1/f ) Noise 1956.5.4 Clock Edge Divider Effects 2006.5.5 VHDL Model Realization of a DCO 2016.5.6 Support of Physical KDCO 2026.6 Modeling Metastability in Flip-Flops 2036.7 Simulation Results 2066.7.1 Time-Domain Simulations 2066.7.2 Frequency-Deviation Simulations 2076.7.3 Phase-Domain Simulations of Transmitters 2096.7.4 Synthesizer Phase-Noise Simulations 2096.8 Summary 2127 IMPLEMENTATION AND EXPERIMENTAL RESULTS 2137.1 DSP and Its RF Interface to DRP 2137.2 Transmitter Core Implementation 2147.3 IC Chip 2167.4 Evaluation Board 2187.5 Measurement Equipment 2187.6 GFSK Transmitter Performance 2197.7 Synthesizer Performance 2217.8 Synthesizer Switching Transients 2247.9 DSP-Driven Modulation 2257.10 Performance Summary 2267.11 Summary 227APPENDIX A: SPURS DUE TO DCO SWITCHING 228A.1 Spurs Due to DCO Modulation 229APPENDIX B: GAUSSIAN PULSE-SHAPING FILTER 232APPENDIX C: VHDL SOURCE CODE 237C.1 DCO Level 2 237C.2 Period-Controlled Oscillator 239C.3 Tactical Flip-Flop 241C.4 TDC Pseudo-Thermometer Output Decoder 243REFERENCES 247INDEX 253