Luciano Lavagno received his Ph.D. in EECS from U.C. Berkeley in 1992 and from Politecnico di Torino in 1993. He co-authored two books on asynchronous circuit design, a book on hardware/software co-design of embedded systems, and over 250 scientific papers. Between 1993 and 2000 he was the architect of the POLIS project, a cooperation between U.C. Berkeley, Cadence Design Systems, Magneti Marelli and Politecnico di Torino, which developed a complete hardware/software co-design environment for control-dominated embedded systems. Between 2003 and 2014 he was one of the creators and architects of the Cadence CtoSilicon high-level synthesis system. Since 2011, Dr. Lavagno has been a full professor with Politecnico di Torino, Italy. He has served on the technical committees of several international conferences in his field (e.g. DAC, DATE, ICCAD, ICCD, ASYNC, CODES) as well as various workshops and symposia and is a senior member of IEEE. He has also been an associate editor of IEEE TCAS and ACM TECS. His research interests include the high-level synthesis of digital circuits and the acceleration of Machine learning algorithms using Field Programmable Gate Arrays.Grant E. Martin retired from his position as a distinguished engineer at Cadence Design Systems, Inc., San Jose, California, USA, in 2023. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/Bell-Northern Research in Canada for 10 years; Cadence Design Systems for 9 years, eventually becoming a fellow in their labs; and Tensilica for 9 years. He rejoined Cadence in 2013 when it acquired Tensilica, and has been there since, working in the Tensilica part of the Cadence Intellectual Property Group. He received his bachelor’s and master’s degrees in mathematics (combinatorics and optimization) from the University of Waterloo, Ontario, Canada, in 1977 and 1978. Grant has coauthored and coedited several books, including the first-ever book on system-on-chip (SoC) design published in Russian. He has also presented many papers, talks, and tutorials, and participated in panels at several major conferences. He cochaired the VSI Alliance Embedded Systems Study Group in the summer of 2001 and was co-chair of the Design Automation Conference Technical Program Committee for Methods for 2005 and 2006. He is a senior member of IEEE. Although retired, he continues to have an interest in system-level design, IP-based design of system-on-chip, platform-based design, DSP, baseband and image processing, and embedded software.

• 1. Overview. 2. Integrated Circuit Design Process and Electronic Design Automation. Section 1. System-Level Design. 3. Tools and Methodologies for System-Level Design. 4. System-Level Specification and Modeling Languages. 5. SoC Block-Based Design and IP Assembly. 6. Performance Evaluation Methods for Multiprocessor System-on-Chip Designs. 7. System-Level Power Management. 8. Processor Modeling and Design Tools. 9. Models and Tools for Complex Embedded Software and Systems. 10. System-Level Design. 11. High-Level Synthesis. Section II. Micro-Architecture Design. 12. SystemC Models and Annotations. 13. Micro-Architectural and System-Level Power Estimation and Optimization. 14. Design Planning. Section III. Logic Verification. 15. Design and Verification Languages. 16. Digital Simulation. 17. Gearing up with Digital Twins: From SoC Shift Left to System-of-Systems Quality. 18. Assertion-Based Verification. 19. Hardware-Assisted Verification and Software Development. 20. Formal Property Verification. Section IV. Test. 21. Design-for-Test. 22. Automatic Test Pattern Generation. 23. Analog and Mixed-Signal Test.

Luciano Lavagno received his Ph.D. in EECS from U.C. Berkeley in 1992 and from Politecnico di Torino in 1993. He co-authored two books on asynchronous circuit design, a book on hardware/software co-design of embedded systems, and over 250 scientific papers. Between 1993 and 2000 he was the architect of the POLIS project, a cooperation between U.C. Berkeley, Cadence Design Systems, Magneti Marelli and Politecnico di Torino, which developed a complete hardware/software co-design environment for control-dominated embedded systems. Between 2003 and 2014 he was one of the creators and architects of the Cadence CtoSilicon high-level synthesis system. Since 2011, Dr. Lavagno has been a full professor with Politecnico di Torino, Italy. He has served on the technical committees of several international conferences in his field (e.g. DAC, DATE, ICCAD, ICCD, ASYNC, CODES) as well as various workshops and symposia and is a senior member of IEEE. He has also been an associate editor of IEEE TCAS and ACM TECS. His research interests include the high-level synthesis of digital circuits and the acceleration of Machine learning algorithms using Field Programmable Gate Arrays.Grant E. Martin retired from his position as a distinguished engineer at Cadence Design Systems, Inc., San Jose, California, USA, in 2023. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/Bell-Northern Research in Canada for 10 years; Cadence Design Systems for 9 years, eventually becoming a fellow in their labs; and Tensilica for 9 years. He rejoined Cadence in 2013 when it acquired Tensilica, and has been there since, working in the Tensilica part of the Cadence Intellectual Property Group. He received his bachelor’s and master’s degrees in mathematics (combinatorics and optimization) from the University of Waterloo, Ontario, Canada, in 1977 and 1978. Grant has coauthored and coedited several books, including the first-ever book on system-on-chip (SoC) design published in Russian. He has also presented many papers, talks, and tutorials, and participated in panels at several major conferences. He cochaired the VSI Alliance Embedded Systems Study Group in the summer of 2001 and was co-chair of the Design Automation Conference Technical Program Committee for Methods for 2005 and 2006. He is a senior member of IEEE. Although retired, he continues to have an interest in system-level design, IP-based design of system-on-chip, platform-based design, DSP, baseband and image processing, and embedded software.

• 1. Overview. 2. Integrated Circuit Design Process and Electronic Design Automation. Section 1. System-Level Design. 3. Tools and Methodologies for System-Level Design. 4. System-Level Specification and Modeling Languages. 5. SoC Block-Based Design and IP Assembly. 6. Performance Evaluation Methods for Multiprocessor System-on-Chip Designs. 7. System-Level Power Management. 8. Processor Modeling and Design Tools. 9. Models and Tools for Complex Embedded Software and Systems. 10. System-Level Design. 11. High-Level Synthesis. Section II. Micro-Architecture Design. 12. SystemC Models and Annotations. 13. Micro-Architectural and System-Level Power Estimation and Optimization. 14. Design Planning. Section III. Logic Verification. 15. Design and Verification Languages. 16. Digital Simulation. 17. Gearing up with Digital Twins: From SoC Shift Left to System-of-Systems Quality. 18. Assertion-Based Verification. 19. Hardware-Assisted Verification and Software Development. 20. Formal Property Verification. Section IV. Test. 21. Design-for-Test. 22. Automatic Test Pattern Generation. 23. Analog and Mixed-Signal Test.

Luciano Lavagno received his Ph.D. in EECS from U.C. Berkeley in 1992 and from Politecnico di Torino in 1993. He co-authored two books on asynchronous circuit design, a book on hardware/software co-design of embedded systems, and over 250 scientific papers. Between 1993 and 2000 he was the architect of the POLIS project, a cooperation between U.C. Berkeley, Cadence Design Systems, Magneti Marelli and Politecnico di Torino, which developed a complete hardware/software co-design environment for control-dominated embedded systems. Between 2003 and 2014 he was one of the creators and architects of the Cadence CtoSilicon high-level synthesis system. Since 2011, Dr. Lavagno has been a full professor with Politecnico di Torino, Italy. He has served on the technical committees of several international conferences in his field (e.g. DAC, DATE, ICCAD, ICCD, ASYNC, CODES) as well as various workshops and symposia and is a senior member of IEEE. He has also been an associate editor of IEEE TCAS and ACM TECS. His research interests include the high-level synthesis of digital circuits and the acceleration of Machine learning algorithms using Field Programmable Gate Arrays.Grant E. Martin retired from his position as a distinguished engineer at Cadence Design Systems, Inc., San Jose, California, USA, in 2023. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/Bell-Northern Research in Canada for 10 years; Cadence Design Systems for 9 years, eventually becoming a fellow in their labs; and Tensilica for 9 years. He rejoined Cadence in 2013 when it acquired Tensilica, and has been there since, working in the Tensilica part of the Cadence Intellectual Property Group. He received his bachelor’s and master’s degrees in mathematics (combinatorics and optimization) from the University of Waterloo, Ontario, Canada, in 1977 and 1978. Grant has coauthored and coedited several books, including the first-ever book on system-on-chip (SoC) design published in Russian. He has also presented many papers, talks, and tutorials, and participated in panels at several major conferences. He cochaired the VSI Alliance Embedded Systems Study Group in the summer of 2001 and was co-chair of the Design Automation Conference Technical Program Committee for Methods for 2005 and 2006. He is a senior member of IEEE. Although retired, he continues to have an interest in system-level design, IP-based design of system-on-chip, platform-based design, DSP, baseband and image processing, and embedded software.

• 1. Overview. 2. Integrated Circuit Design Process and Electronic Design Automation. Section 1. System-Level Design. 3. Tools and Methodologies for System-Level Design. 4. System-Level Specification and Modeling Languages. 5. SoC Block-Based Design and IP Assembly. 6. Performance Evaluation Methods for Multiprocessor System-on-Chip Designs. 7. System-Level Power Management. 8. Processor Modeling and Design Tools. 9. Models and Tools for Complex Embedded Software and Systems. 10. System-Level Design. 11. High-Level Synthesis. Section II. Micro-Architecture Design. 12. SystemC Models and Annotations. 13. Micro-Architectural and System-Level Power Estimation and Optimization. 14. Design Planning. Section III. Logic Verification. 15. Design and Verification Languages. 16. Digital Simulation. 17. Gearing up with Digital Twins: From SoC Shift Left to System-of-Systems Quality. 18. Assertion-Based Verification. 19. Hardware-Assisted Verification and Software Development. 20. Formal Property Verification. Section IV. Test. 21. Design-for-Test. 22. Automatic Test Pattern Generation. 23. Analog and Mixed-Signal Test.