Yamin Li, Professor, Department of Computer Science, Hosei University, Tokyo, Japan.Professor Li received his PhD in computer science from Tsinghua University in 1989. His research interests include computer arithmetic algorithms, computer architecture, CPU design, and parallel & distributed computing. He is a senior member of the IEEE and a member of the IEEE Computer Society. Professor Li has taught the courses of "Logic Circuit Design", "Assembly Language Programming", "Computer Organization and Design", "CPU Design in Verilog HDL", "Computer Architecture", and "Parallel & Distributed Systems" for more than 20 years, and has used FPGA boards and CAD/CAE tools to teach these courses since 1993. He has published more than 100 journal and conference papers, and developed a square root circuit at low cost and published it in IEEE ICCD'96 and ICCD'97.

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• List of Figures xvList of Tables xxviiPreface xxix1 Computer Fundamentals and Performance Evaluation 12 A Brief Introduction to Logic Circuits and Verilog HDL 193 Computer Arithmetic Algorithms and Implementations 634 Instruction Set Architecture and ALU Design 1115 Single-Cycle CPU Design in Verilog HDL 1436 Exceptions and Interrupts Handling and Design in Verilog HDL 1707 Multiple-Cycle CPU Design in Verilog HDL 1928 Design of Pipelined CPU with Precise Interrupt in Verilog HDL 2129 Floating-Point Algorithms and FPU Design in Verilog HDL 26610 Design of Pipelined CPU with FPU in Verilog HDL 32311 Memory Hierarchy and Virtual Memory Management 35312 Design of Pipelined CPU with Caches and TLBs in Verilog HDL 38613 Multithreading CPU and Multicore CPU Design in Verilog HDL 42514 Input/Output Interface Controller Design in Verilog HDL 44315 High-Performance Computers and Interconnection Networks 509Bibliography 536Index 539

Yamin Li, Professor, Department of Computer Science, Hosei University, Tokyo, Japan.Professor Li received his PhD in computer science from Tsinghua University in 1989. His research interests include computer arithmetic algorithms, computer architecture, CPU design, and parallel & distributed computing. He is a senior member of the IEEE and a member of the IEEE Computer Society. Professor Li has taught the courses of "Logic Circuit Design", "Assembly Language Programming", "Computer Organization and Design", "CPU Design in Verilog HDL", "Computer Architecture", and "Parallel & Distributed Systems" for more than 20 years, and has used FPGA boards and CAD/CAE tools to teach these courses since 1993. He has published more than 100 journal and conference papers, and developed a square root circuit at low cost and published it in IEEE ICCD'96 and ICCD'97.

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• List of Figures xvList of Tables xxviiPreface xxix1 Computer Fundamentals and Performance Evaluation 12 A Brief Introduction to Logic Circuits and Verilog HDL 193 Computer Arithmetic Algorithms and Implementations 634 Instruction Set Architecture and ALU Design 1115 Single-Cycle CPU Design in Verilog HDL 1436 Exceptions and Interrupts Handling and Design in Verilog HDL 1707 Multiple-Cycle CPU Design in Verilog HDL 1928 Design of Pipelined CPU with Precise Interrupt in Verilog HDL 2129 Floating-Point Algorithms and FPU Design in Verilog HDL 26610 Design of Pipelined CPU with FPU in Verilog HDL 32311 Memory Hierarchy and Virtual Memory Management 35312 Design of Pipelined CPU with Caches and TLBs in Verilog HDL 38613 Multithreading CPU and Multicore CPU Design in Verilog HDL 42514 Input/Output Interface Controller Design in Verilog HDL 44315 High-Performance Computers and Interconnection Networks 509Bibliography 536Index 539

Yamin Li, Professor, Department of Computer Science, Hosei University, Tokyo, Japan.Professor Li received his PhD in computer science from Tsinghua University in 1989. His research interests include computer arithmetic algorithms, computer architecture, CPU design, and parallel & distributed computing. He is a senior member of the IEEE and a member of the IEEE Computer Society. Professor Li has taught the courses of "Logic Circuit Design", "Assembly Language Programming", "Computer Organization and Design", "CPU Design in Verilog HDL", "Computer Architecture", and "Parallel & Distributed Systems" for more than 20 years, and has used FPGA boards and CAD/CAE tools to teach these courses since 1993. He has published more than 100 journal and conference papers, and developed a square root circuit at low cost and published it in IEEE ICCD'96 and ICCD'97.

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• List of Figures xvList of Tables xxviiPreface xxix1 Computer Fundamentals and Performance Evaluation 12 A Brief Introduction to Logic Circuits and Verilog HDL 193 Computer Arithmetic Algorithms and Implementations 634 Instruction Set Architecture and ALU Design 1115 Single-Cycle CPU Design in Verilog HDL 1436 Exceptions and Interrupts Handling and Design in Verilog HDL 1707 Multiple-Cycle CPU Design in Verilog HDL 1928 Design of Pipelined CPU with Precise Interrupt in Verilog HDL 2129 Floating-Point Algorithms and FPU Design in Verilog HDL 26610 Design of Pipelined CPU with FPU in Verilog HDL 32311 Memory Hierarchy and Virtual Memory Management 35312 Design of Pipelined CPU with Caches and TLBs in Verilog HDL 38613 Multithreading CPU and Multicore CPU Design in Verilog HDL 42514 Input/Output Interface Controller Design in Verilog HDL 44315 High-Performance Computers and Interconnection Networks 509Bibliography 536Index 539