Understanding Delta-Sigma Data Converters

Shanthi Pavan is a Professor of electrical engineering at the Indian Institute of Technology, India, and has been the Editor-In-Chief of the IEEE Transactions on Circuits and Systems, and a Distinguished Lecturer of the IEEE Solid State Circuits Society.  He is a Fellow of the Indian National Academy of Engineering.Richard Schreier was a Division Fellow in Analog Devices Inc. and an Adjunct Professor at the University of Toronto, Canada, when he retired in 2016. From 1991-1997 he was a Professor at Oregon State University.He was named an IEEE Fellow in 2015.Gabor Temes is a Distinguished Professor Emeritus of the University of California, and Professor in the School of Electrical Engineering and Computer Science at Oregon State University, USA.  He is an IEEE Life Fellow and a member of the US National Academy of Engineering.

• Preface xiii 1 The Magic of Delta-Sigma Modulation 11.1 The Need for Oversampling Converters 11.2 Nyquist and Oversampling Conversion by Example 31.3 Higher-Order Single-Stage Noise-Shaping Modulators 111.4 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators 121.5 Mismatch Shaping in Multi-Bit Delta-Sigma Modulators 141.6 Continuous-Time Delta-Sigma Modulation 151.7 Bandpass Delta-Sigma Modulators 171.8 Incremental Delta-Sigma Converters 181.9 Delta-Sigma Digital-to-Analog Converters 181.10 Decimation and Interpolation 191.11 Specifications and Figures of Merit 191.12 Early History, Performance, and Architectural Trends 21References 252 Sampling, Oversampling, and Noise-Shaping 272.1 A Review of Sampling 282.2 Quantization 302.3 Quantization Noise Reduction by Oversampling 392.4 Noise-Shaping 422.5 Nonlinear Aspects of the First-Order Delta-Sigma Modulator 522.6 MOD1 with DC Excitation 542.7 Alternative Architectures: The Error-Feedback Structure 602.8 The Road Ahead 60References 613 Second-Order Delta-Sigma Modulation 633.1 Simulation of MOD2 673.2 Nonlinear Effects in MOD2 703.3 Stability of MOD2 733.4 Alternative Second-Order Modulator Structures 773.5 Generalized Second-Order Structures 803.6 Conclusions 82References 824 High-Order Delta-Sigma Modulators 834.1 Signal-Dependent Stability of Delta-Sigma Modulators 854.2 Improving MSA in High-Order Delta-Sigma Converters 924.3 Systematic NTF Design 954.4 Noise Transfer Functions with Optimally Spread Zeros 974.5 Fundamental Aspects of Noise Transfer Functions 984.6 High-Order Single-Bit Delta-Sigma Data Converters 1004.7 Loop Filter Topologies for Discrete-Time Delta-Sigma Converters 1044.8 State-Space Description of Delta-Sigma Loops 1144.9 Conclusions 115References 1155 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators 1175.1 Multi-Stage Modulators 1175.2 Cascade (MASH) Modulators 1205.3 Noise Leakage in Cascade Modulators 1235.4 The Sturdy-MASH Architecture 1265.5 Noise-Coupled Architectures 1285.6 Cross-Coupled Architectures 1315.7 Conclusions 131References 1336 Mismatch-Shaping 1356.1 The Mismatch Problem 1356.2 Random Selection and Rotation 1366.3 Implementation of Rotation 1416.4 Alternative Mismatch-Shaping Topologies 1456.5 High-Order Mismatch-Shaping 1516.6 Generalizations 1566.7 Transition-Error Shaping 1586.8 Conclusions 162References 1627 Circuit Design for Discrete-Time Delta-Sigma ADCs 1657.1 SCMOD2: A Second-Order Switched-Capacitor ADC 1657.2 High-Level Design 1667.3 Switched-Capacitor Integrator 1687.4 Capacitor Sizing 1747.5 Initial Verification 1767.6 Amplifier Design 1787.7 Intermediate Verification 1867.8 Switch Design 1917.9 Comparator Design 1917.10 Clocking 1957.11 Full-System Verification 1977.12 High-Order Modulators 2017.13 Multi-Bit Quantization 2037.14 Switch Design Revisited 2077.15 Double Sampling 2097.16 Gain-Boosting and Gain-Squaring 2117.17 Split-Steering and Amplifier Stacking 2127.18 Noise in Switched-Capacitor Circuits 2177.19 Conclusions 221References 2218 Continuous-Time Delta-Sigma Modulation 2238.1 CT-MOD1 2248.2 STF of CT-MOD1 2308.3 Second-Order Continuous-Time Delta-Sigma Modulation 2348.4 High-Order Continuous-Time Delta-Sigma Modulators 2398.5 Loop-Filter Topologies 2468.6 Continuous-Time Delta-Sigma Modulators with Complex NTF Zeros 2498.7 Modeling of Continuous-Time Delta-Sigma Modulators for Simulation 2508.8 Dynamic-Range Scaling 2538.9 Design Example 2558.10 Conclusions 258References 2589 Nonidealities in Continuous-Time Delta-Sigma Modulators 2599.1 Excess Loop Delay 2599.2 Time-Constant Variations of the Loop Filter 2719.3 Clock Jitter in Delta-Sigma Modulators 2739.4 Addressing Clock Jitter in Continuous-Time Delta-Sigma Modulators 2859.5 Mitigating Clock Jitter Using FIR Feedback 2879.6 Comparator Metastability 2939.7 Conclusions 298References 29810 Circuit Design for Continuous-Time Delta-Sigma Modulators 30110.1 Integrators 30210.2 The Miller-Compensated OTA-RC Integrator 30510.3 The Feedforward-Compensated OTA-RC Integrator 30610.4 Stability of Feedforward Amplifiers 30910.5 Device Noise in Continuous-Time Delta-Sigma Modulators 31210.6 ADC Design 31610.7 Feedback DAC Design 32010.8 Systematic Design Centering 33110.9 Loop-Filter Nonlinearities in Continuous-Time Delta-Sigma Modulators 33810.10 Case Study of a 16-Bit Audio Continuous-Time Delta-Sigma Modulator34610.11 Measurement Results 35810.12 Summary 359References 36011 Bandpass and Quadrature Delta-Sigma Modulation 36311.1 The Need for Bandpass Conversion 36311.2 System Overview 36611.3 Bandpass NTFs 36711.4 Architectures for Bandpass Delta-Sigma Modulators 37211.5 Bandpass Modulator Example 38011.6 Quadrature Signals 39111.7 Quadrature Modulation 39611.8 Polyphase Signal Processing 40211.9 Conclusions 404References 40512 Incremental Analog-to-Digital Converters 40712.1 Motivation and Trade-Offs 40712.2 Analysis and Design of Single-Stage IADCs 40812.3 Digital Filter Design for Single-Stage IADCs 41112.4 Multiple-Stage IADCs and Extended Counting ADCs 41512.5 IADC Design Examples 41612.6 Conclusions 422References 42313 Delta-Sigma DACs 42513.1 System Architectures for Delta-Sigma DACs 42513.2 Loop Configurations for Delta-Sigma DACs 42713.3 Delta-Sigma DACs Using Multi-Bit Internal DACs 43113.4 Interpolation Filtering for Delta-Sigma DACs 43813.5 Analog Post-Filters for Delta-Sigma DACs 44113.6 Conclusions 449References 44914 Interpolation and Decimation Filters 45114.1 Interpolation Filtering 45214.2 Example Interpolation Filter 45614.3 Decimation Filtering 46114.4 Example Decimation Filter 46314.5 Halfband Filters 46714.5.1 Saramäki Halfband Filter 46914.6 Decimation for Bandpass Delta-Sigma ADCs 47114.7 Fractional Rate Conversion 47214.8 Summary 480References 480A Spectral Estimation 483A.1 Windowing 484A.2 Scaling and Noise Bandwidth 488A.3 Averaging 491A.4 An Example 493A.5 Mathematical Background 495References 498B The Delta-Sigma Toolbox 499C Linear Periodically Time-Varying Systems 539C.1 Linearity and Time (In)variance 539C.2 Linear Time-Varying Systems 541C.3 Linear Periodically Time-Varying (LPTV) Systems 543C.4 LPTV Systems with Sampled Outputs 547References 559Index 561