Multicore Technology

Architecture, Reconfiguration, and Modeling

AvMuhammad Yasir Qadri,Stephen J. Sangwine

Häftad, Engelska, 2017

Del i serien Embedded Multi-Core Systems

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Beskrivning

The saturation of design complexity and clock frequencies for single-core processors has resulted in the emergence of multicore architectures as an alternative design paradigm. Nowadays, multicore/multithreaded computing systems are not only a de-facto standard for high-end applications, they are also gaining popularity in the field of embedded computing. The start of the multicore era has altered the concepts relating to almost all of the areas of computer architecture design, including core design, memory management, thread scheduling, application support, inter-processor communication, debugging, and power management. This book gives readers a holistic overview of the field and guides them to further avenues of research by covering the state of the art in this area. It includes contributions from industry as well as academia.

Produktinformation

Utgivningsdatum:2017-10-12
Mått:156 x 234 x undefined mm
Vikt:453 g
Format:Häftad
Språk:Engelska
Serie:Embedded Multi-Core Systems
Antal sidor:491
Förlag:Taylor & Francis Ltd
ISBN:9781138072503

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Muhammad Yasir Qadri, Stephen J. Sangwine

Innehållsförteckning

Architecture and Design Flow: MORA: High-Level FPGA Programming Using a Many-Core Framework. Implementing Time-Constrained Applications on a Predictable MPSoc. SESAM: A Virtual Prototyping Solution to Design Multicore Architectures. Parallelism and Optimization: Verified Multicore Parallelism Using Atomic Verifiable Operations. Accelerating Critical Section Execution with Multicore Architectures. Memory Systems: TMbox: A Flexible and Reconfigurable Hybrid Transactional Memory System. EM2. CAFÉ: Cache-Aware Fair and Efficient Scheduling for CMPs. Debugging: Software Debugging Infrastructure for Multicore Systems-on-Chip. Networks-on-Chip: On Chip Interconnects for Multicore Architectures. Routing in Multicore NoCs. Efficient Topologies for 3-D Networks-on-Chip. Network-on-Chip Performance Evaluation Using an Analytical Method. Bibliography. Index.

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