Incremental Data Converters for Sensor Interfaces

Chia-Hung Chen, PhD, is an Assistant Professor with the Department of Electrical and Computer Engineering at National Yang Ming Chiao Tung University, Hsinchu, Taiwan. His research interests are in the design of precision analog circuits and energy-efficient data converters. Gabor C. Temes, PhD, is a Professor with the School of Electrical Engineering and Computer Science at Oregon State University, Corvallis, USA. He has coedited and coauthored many papers and books; the most recent one being Understanding Delta-Sigma Data Converters, 2nd Edition (2016).

• About the Authors ixPreface xiAbstract & Keywords xiii1 Fundamentals of Analog-to-Digital Data Converters (ADCs) 11.1 Performance Parameters for Analog-to-Digital Converters 11.2 Algorithms and Architectures for Analog-to-Digital Converters 41.2.1 Dual-Slope (Integrating) ADCs 51.2.2 Delta-Sigma A/D Converters 61.2.3 Successive Approximation A/D Converters 111.2.4 Flash A/D Converter 131.2.5 Incremental A/D Converter 14References 152 Delta-Sigma ADCs 172.1 Sampled-DataΔΣ ADCs 182.2 Loop Filter Structures and Circuits for Sampled-Data ΔΣ ADCs 202.3 Optimization of Zeros and Poles for Sampled-Data ΔΣ ADCs 222.4 Limitations on the Performance of Sampled-Data ΔΣ ADCs 232.5 Multistage Sampled-Data ΔΣ ADCs 262.6 Continuous-Time ΔΣ ADCs 272.7 Advantages and Limitations of Continuous-Time ΔΣ ADCs 31References 363 Single-Stage Incremental Analog-to-Digital Converters 393.1 The First-Order IADC 393.2 Higher-Order Single-Stage IADCs 423.2.1 Analysis and Design of a Second-Order IADC 423.2.2 The Design of Higher-Order IADCs 443.2.3 IADC Circuit Techniques 463.2.4 Comparison of IADCs and ΔΣ ADCs 473.3 Decimation Filter and the Overall Design of IADCs 483.3.1 Cascade-of-Integrators (CoI) 483.3.2 Thermal Noise 483.3.3 Optimized Digital Filter Design for a Single-Stage IADC 493.3.4 Multiple-Stage IADCs and Extended Counting ADCs 523.4 Estimation of Power Consumption 533.4.1 Power Consumption for Small Signal Settling 533.4.2 Power Consumption for Slewing 553.4.3 An Example 56References 574 Multistage and Extended Counting Incremental Analog-to-Digital Converters 594.1 Multistage Noise Shaping (MASH) Incremental ADCs 594.1.1 The Design of MASH IADCs 594.1.2 Trade-Offs in the Design of MASH IADCs 614.1.3 Hybrid Schemes for an IADC and a Nyquist-Rate ADC 624.1.4 Extended Counting with Hardware Sharing 644.2 Design Examples 664.2.1 IADC with Two-Capacitor Counting 664.2.2 Switched-Capacitor Implementation of the Example IADC 694.2.3 Nonideal Effects 724.2.4 Measured Performance 734.3 The Zoom Incremental ADC 774.3.1 Two-Stage 0-L IADCs 774.4 Zoom ADC Design Example 794.4.1 Nonideal Effects 804.4.2 Measured Performance 81References 835 Design Examples 875.1 A Third-Order 22-Bit IADC 875.2 A 16-Bit Multistep IADC with Single-Opamp Multi-Slope Extended Counting 925.3 Multistep IADCs 1005.3.1 Two-Step IADCs 1005.3.2 Switched-Capacitor Circuitry 1045.3.3 Measured Performance 1075.3.4 A Two-Step Third-Order IADC 1085.3.5 Conclusion 1105.4 A Hybrid Continuous-Time Incremental and SAR Two-Step ADC with 90.5 dB Dynamic Range Over 1 MHz Bandwidth 1115.5 A Multistage Multistep IADC 1185.5.1 Design of a MASH 2-1 IADC 1185.5.2 An IADC2-1 Versus a MASH 2-1 ΔΣ ADC 1205.5.3 Noise Consideration for Higher-Order IADCs 1215.5.4 The Proposed Multistage Multistep IADC 1225.5.5 Circuit Implementation 1275.5.6 Measured Performance 1325.5.7 Conclusion 137References 137Index 143