The design process of digital circuits is often carried out in individual steps, like logic synthesis, mapping, and routing. Since the complete process is too complex, it has been split up in several - more or less independent - phases. During the latter half of the 20th century, powerful algorithms were developed to find optimal solutions for each of these steps, though these are rarely used. This neglect leads to quality loss, as optimized netlists fit badly onto the target architecture. Since the resulting circuits are often far from being optimal and insufficient regarding the optimization criteria, several iterations of the complete design process have to be carried out to get high quality results. This is a very time consuming and costly process. For this reason, the idea of one-pass synthesis was explored. There are two main approaches how to guarantee that a design is "right first time": combining levels that were split before, for example, to use layout information already during the logic synthesis phase; and restricting the optimization in one level such that it better fits to the next one.Several approaches in these two directions have been presented and new techniques are under development at the beginning of the 21st century. This title describes the paradigm that is used in one-pass synthesis and presents examples for the two techniques above. Theoretical and practical aspects are discussed and minimization algorithms are given.
