Noise Coupling in System-on-Chip

Thomas Noulis is an Assistant Professor in the Physics Department at Aristotle University, in the Electronics Laboratory. From 2012 to 2015, he worked with INTEL Corp., as a Staff RFMS Engineer, in the Mobile & Communications Group in Munich-Germany, where he specialized on 14nm & 28nm design, modeling/characterization, crosstalk and in SoC product active area minimization & migration. Before joining INTEL, from May 2008 to March 2012, Dr. Noulis was with HELIC Inc, initially as Analog/RF IC designer and then as an R&D Engineer specializing in substrate coupling, signal and noise integrity and analog/RFIC design. Thomas Noulis holds a B.Sc. Degree in Physics (2003), a M.Sc. Degree in Electronics Engineering (2005), and a Ph.D in the "Design of signal processing integrated circuits" (2009) from Aristotle Univ. of Thessaloniki, Greece and in collaboration with LAAS (Toulouse-France). From 2004 to 2009, he participated as a principal researcher in multiple European and National research projects related to Space Application and Nuclear Spectroscopy IC design; simultaneously, from 2004 to 2010, he also collaborated as a Visiting/Adjunct Professor with Universities and Technical Institutes. Dr. Noulis is the main author of more than 40 publications, in journals, conferences and scientific book chapters. He holds one French and World patent. His work received more than 50 citations. He is an active reviewer of multiple international journals and has given multiple invited presentations in European Research Institutes on crosstalk and Rad-IC design. Dr. Noulis has been awarded for his research activity by conferences and research organizations and can be reached at t.noulis@gmail.com.

"This is one of the most modern books related on the noise coupling in modern Systems on Chip (SoC) design. It addresses the state of the art in the SoC design, covering a wide range of topics, including novel methodologies to identify noise coupling in silicon, interconnect and package helping locate potential noise issues, both before tape‐out and even earlier in the design process. The coupling mechanisms are addressed from silicon device level to package and printed circuit board level and from the kHz region until the mm Wave frequency region. Special focus is provided in 3D integration and on Through Silicon Vias coupling mechanisms. In addition, emerging coupling topics are addressed such as thermal and optical interconnects performance, power delivery networks, electro-thermal considerations onto 3D integration and 3D floor planning based on thermal interactions.A strong point of the book is that it has been written by a mixture of industrial experts and academic professors and researchers, providing in-depth theoretical background and discussion of the most important practical aspects. Therefore, this book will be a powerful tool for designers involved with high performance SoC design in both 2D and 3D ICs. Using this book, we able to utilize innovative coupling analysis flow and modeling, addressing all related needs, to analyze noise components, propagating not just through the substrate, but also through the parasitic interconnect and package and to identify substrate coupling noise contributors, levels and transfer functions."— Costas Psychalinos, University of Patras, Greece"This book addresses noise coupling in integrated systems, which is a topic mostly widespread in industrial developments…This book could contribute to developing a widespread culture about how to deal with noise coupling in modern integrated systems."—Domenico Zito, Aarhus University, Denmark

• System on Chip Substrate Crosstalk Modeling and Simulation Flow. Substrate Induced Signal Integrity in 2D and 3D Ics. TSV-to-Substrate Noise Coupling in 3-D Systems. 3-D Interconnects with IC’s Stack Global Electrical Context Consideration. Modeling of On-Chip Power Distribution Network. Printed Circuit Board Integration of SoC Packages and Signal Integrity Issues at Board Level. Modeling and Characterization of TSV-Induced Noise Coupling. Layout strategies for substrate crosstalk reduction in low cost CMOS processes. Wireless Communications System on Chip substrate noise real time sensing. System-on-Chip Substrate Crosstalk Measurement Techniques. IC Floorplanning Based on Thermal Interactions. A Unified Method for Calculating Parasitic Capacitive and Resistive Coupling in VLSI Circuits. Coupling through substrate for millimeter wave frequencies. Paradigm Shift of On-Chip Interconnects from Electrical to Optical. Electro-Thermal Considerations dedicated to 3-D Integration; Noise Coupling.