Multi-Processor System-on-Chip 2

Liliana Andrade is Associate Professor at TIMA Lab, Université Grenoble Alpes in France. She received her PhD in Computer Science, Telecommunications and Electronics from Université Pierre et Marie Curie in 2016. Her research interests include system-level modeling/validation of systems-on-chips, and the acceleration of heterogeneous systems simulation. Frédéric Rousseau is Full Professor at TIMA Lab, Université Grenoble Alpes in France. His research interests concern Multi-Processor Systems-on-Chip design and architecture, prototyping of hardware/software systems including reconfigurable systems and highlevel synthesis for embedded systems.

• Foreword xiAhmed JERRAYAAcknowledgments xiiiLiliana ANDRADE and Frédéric ROUSSEAUPart 1. MPSoC for Telecom 1Chapter 1. From Challenges to Hardware Requirements for Wireless Communications Reaching 6G 3Stefan A. DAMJANCEVIC, Emil MATUS, Dmitry UTYANSKY, Pieter VAN DER WOLF and Gerhard P. FETTWEIS1.1. Introduction 41.2. Breadth of workloads 61.2.1. Vision, trends and applications 61.2.2. Standard specifications 81.2.3. Outcome of workloads 131.3. GFDM algorithm breakdown 141.3.1. Equation 151.3.2. Dataflow processing graph and matrix representation 151.3.3. Pseudo-code 161.4. Algorithm precision requirements and considerations 181.5. Implementation 211.5.1. Implementation considerations 231.5.2. Design space exploration 231.5.3. Measurements for low-end and high-end use cases 261.6. Conclusion 281.7. Acknowledgments 291.8. References 29Chapter 2. Towards Tbit/s Wireless Communication Baseband Processing: When Shannon meets Moore 33Matthias HERRMANN and Norbert WEHN2.1. Introduction 342.2. Role of microelectronics 362.3. Towards 1 Tbit/s throughput decoders 372.3.1. Turbodecoder 392.3.2. LDPC  decoder 412.3.3. Polar decoder 412.4. Conclusion 432.5. Acknowledgments 432.6. References 43Part 2. Application-specific MPSoC Architectures 47Chapter 3. Automation for Industry 4.0 by using Secure LoRaWAN Edge Gateways 49Marcello COPPOLA and George KORNAROS3.1. Introduction 503.2. Security in IIoT 523.3. LoRaWAN security in IIoT 533.4. Threatmodel 553.4.1. LoRaWAN attack model 553.4.2. IIoT node attack model 563.5. Trusted boot chain with STM32MP1 573.5.1. Trust base of node 573.5.2. Trusted firmware inSTM32MP1 573.5.3. Trusted execution environments and OP-TEE 583.5.4. OP-TEE scheduling considerations 603.5.5. OP-TEEmemorymanagement 603.5.6. OP-TEE clientAPI 613.5.7.TEE internal coreAPI 623.5.8. Root and chain of trust 623.5.9. Hardware unique key 623.5.10.  Secure clock 633.5.11. Cryptographic operations 633.6. LoRaWAN gateway  withSTM32MP1 643.7. Discussion and future scope 653.8. Acknowledgments 663.9. References 66Chapter 4. Accelerating Virtualized Distributed NVMe Storage in Hardware 69Julian CHESTERFIELD and Michail FLOURIS4.1. Introduction 704.1.1. Virtualization and traditional hypervisors 714.1.2. Hyperconverged versus disaggregated cloud architectures 724.1.3. NVMe flash storage 744.2. Motivation:NVMe storage for the cloud 754.2.1. Motivation for a new hypervisor 754.2.2. Motivation for accelerating disaggregated storage 764.3. Design 774.3.1. Optimizing the hypervisor I/O operations 774.3.2. Design of accelerated disaggregated storage 804.4. Implementation 864.4.1. The NexVisor platform 874.4.2. Accelerated disaggregated storage 874.5. Results 904.5.1. Sequential reads 904.5.2.  Sequentialwrites 904.5.3. Sequential reads on one NVMe drive 924.5.4. Networkperformance 924.6. Conclusion 934.7. References 93Chapter 5. Modular and Open Platform for Future Automotive Computing Environment 95Raphaël DAVID, Etienne HAMELIN, Paul DUBRULLE, Shuai LI, Philippe DORE, Alexis OLIVEREAU, Maroun OJAIL, Alexandre CARBON and Laurent LE GARFF5.1. Introduction 965.2. Outline of this approach 985.2.1. Centralized computation, distributed data 985.2.2. Modularity and heterogeneity 995.2.3. Tools for specification, configuration and integration 1015.3. Results 1025.3.1. Hardware platform 1035.3.2. FACE SW architecture 1085.3.3. FACE Tool Suite 1125.4. Use case 1165.4.1. Adaptive braking system 1165.5. Conclusion 1185.6. References 119Chapter 6. Post-Moore Datacenter Server Architecture 123Babak FALSAFI6.1. Introduction 1246.2. Background: today’s blades are from the desktops of the 1980s 1256.3. Memory-centricserverdesign 1276.4. Data management accelerators 1296.5. Integrated network controllers 1306.6. References 131Part 3. Architecture Examples and Tools for MPSoC 135Chapter 7. SESAM: A Comprehensive Framework for Cyber–Physical System Prototyping 137Amir CHARIF, AriefWICAKSANA, Salah-Eddine SAIDI, Tanguy SASSOLAS, Caaliph ANDRIAMISAINA and Nicolas VENTROUX7.1. Introduction 1387.2. An overview of the SESAM platform 1387.2.1. Multi-abstraction system prototyping 1397.2.2. Assessing extra-functional system properties 1407.3. VPSim: fast and easy virtual prototyping 1407.3.1. Writing peripherals in Python 1417.3.2. The Model Provider interface 1427.3.3. QEMU support 1447.3.4. Online simulation monitoring 1467.3.5. Acceleration methods 1467.4. Hybrid prototyping 1477.4.1. Co-simulationmode 1487.4.2. Co-emulationmode 1497.4.3. Runtime performance analysis and debugging features 1497.5.FMI for co-simulation 1507.5.1. Functional mock-up interface 1517.5.2. VPSim integration inFMI co-simulation 1527.6. Conclusion 1557.7. References 155Chapter 8. StaccatoLab: A Programming and Execution Model for Large-scale Dataflow Computing 157Kees VAN BERKEL8.1. Introduction 1588.2. Static dataflow 1618.2.1. Synchronous dataflow 1628.2.2. Cyclo-static dataflow 1668.2.3. Dataflow graph transformations 1678.3. Dynamic dataflow 1688.3.1. Data-dependentdataflow 1688.3.2. Non-determinatedataflow 1728.4. Dataflow execution models 1758.4.1. A brief review of dataflow theory 1758.4.2. The StaccatoLab execution model 1778.5. StaccatoLab 1808.5.1. Dataflow graph description and analysis 1808.5.2. Verilog synthesis 1808.6. Large-scale dataflow computing? 1828.6.1. What kind of applications? 1828.6.2. Why effective? 1838.6.3. Why efficient? 1848.7. Acknowledgments 1858.8. References 185Chapter 9. Smart Cameras and MPSoCs 189Marilyn WOLF9.1. Introduction 1899.2. Early VLSI video processors 1909.3. Video signal processors 1919.4. Accelerators 1939.5. From VSP to  MPSoC 1959.6. Graphics processing units 1979.7. Neural networks and tensor processing units 1979.8. Conclusion 1999.9. References 199Chapter 10. Software Compilation and Optimization Techniques for Heterogeneous Multi-core Platforms 203Weihua SHENG, Jeronimo CASTRILLON and Rainer LEUPERS10.1. Introduction 20410.2. Dataflow modeling 20710.2.1. General concepts 20710.2.2. Process networks 20810.2.3. Cfor process networks 20910.3. Source-to-source-based compiler infrastructure 21410.3.1.Design rationale 21410.3.2. Implementation strategy 21610.4. Software distribution 21810.4.1. KPNanalysis 21910.4.2. Static KPN mapping 22010.4.3. Hybrid KPN mapping 22110.5. Results 22210.5.1.Applications and experiences 22210.5.2. Retargetability 22910.6. Conclusion 23010.7. References 231List of Authors 237Author Biographies 241Index 251