• Fri frakt över 249 kr
  • •
  • Snabba leveranser
  • •
  • Billiga böcker
Kundservice

Du är på sajten för privatpersoner.

Företag, bibliotek eller offentlig verksamhet?

Du handlar på classic.bokus.com, där alla dina funktioner finns intakta.
Till classic.bokus.com
Bokus logotyp. Gå till startsidan.
  • Erbjudanden
  • Nyheter
  • Student
  • Topplistor
  • Barn & ungdom
  • Bokus Play
  • E-böcker
  • Pocketböcker
  • Spel & pussel

10% rabatt på allt med kod: NYSTART10 →

Sidfot

Mina sidor

    Hjälp

    • Kundservice
    • Vanliga frågor och svar
    • Frakt och leverans
    • Retur vid ångerrätt
    • Reklamera vara
    • Betalning
    • Köpvillkor
    • Allmänna villkor
    • Information om webbplatsens tillgänglighet

    Om Bokus

    • Om oss
    • Pressrum
    • För studenter
    • För företag
    • För bibliotek och offentlig verksamhet
    • För leverantörer
    • Hållbarhet

    Populärt

    • Aktuella erbjudanden
    • Presentkort
    • Studentlitteratur
    • Nya böcker
    • Topplistor
    • Signerade böcker
    • Engelska böcker

    Inspiration

    • Boktips
    • BookTok
    • Populära bokserier
    • Barnbokskaraktärer
    • Populära författare
    Logotyp för Bokus
    Följ oss på Facebook (extern länk)Följ oss på Instagram (extern länk)Följ oss på YouTube (extern länk)Följ oss på TikTok (extern länk)
    bokus @ CookiesAnpassa cookiesIntegritetspolicyKöpvillkor
    Till Citymail hemsida (extern länk)Till Budbee hemsida (extern länk)Till Postnord hemsida (extern länk)Till Schenker hemsida (extern länk)Till Early Bird hemsida (extern länk)Till Walleys hemsida (extern länk)
    1. Naturvetenskap och teknik
    2. Teknik och industri
    3. Elektronik och kommunikationer

    Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures

    AvKanchan Manna,Jimson Mathew

    Häftad, Engelska, 2021

    546 kr

    Beställningsvara. Skickas inom 10-15 vardagar. Fri frakt över 249 kr.

    Fler format och utgåvor

    Inbunden

    546 kr

    Beskrivning

    This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.  It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications.  Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems;Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems;Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.

    Produktinformation

    • Utgivningsdatum:2021-01-10
    • Mått:155 x 235 x 10 mm
    • Vikt:277 g
    • Format:Häftad
    • Språk:Engelska
    • Antal sidor:162
    • Förlag:Springer Nature Switzerland AG
    • ISBN:9783030313128

    Utforska kategorier

    • Elektronik och kommunikationer inom Naturvetenskap och teknik
    • Systemvetenskap och AI inom Data och IT

    Mer om författaren

    Kanchan Manna is currently an assistant professor in Department of Computer Science and Engineering, Indian Institute of Technology (IIT) Patna, India. Prior to this, he has worked as a post-doctoral scientist in the Department of Electrical and Computer Engineering (ECE) at George Washington University (GWU), Washington-DC, USA. He earned the MS degree in information technology from Indian Institute of Technology (IIT) Kharagpur, India and the PhD degree in computer science engineering from IIT Kharagpur. His current research interests include Network-on-Chip (NoC) based multicore architecture design, performance and cost evaluation, application mapping in 2D and 3D environments, including thermal-safety, reliability, fault-tolerant and testing. Jimson Mathew is currently an associate professor and head of the Computer Science and Engineering Department, Indian Institute of Technology (IIT) Patna, India. He is also honorary visiting fellow at the Department of Computer Science and Engineering, University of Bristol, UK. He received the Masters in Computer engineering from Nanyang Technological University, Singapore and the Ph.D. degree in computer engineering from the University of Bristol, Bristol, U.K. Prior to this, he has worked with the Centre for Wireless Communications, National University of Singapore, Bell Laboratories Research Lucent Technologies North Ryde, Australia, Royal Institute of Technology KTH, Stockholm, Sweden and Department of Computer Science, University of Bristol, UK. His research interests include fault-tolerant computing, computer arithmetic, hardware security, very large scale integration design and design automation, and design of Network on Chip Architectures. He is the co-author of three published books, and close to 100 publications in international journals and conferences of repute.

    Innehållsförteckning

    • Introduction to Network-on-Chip Designs and Tests.- Iterative Mapping with Through Silicon Via (TSV) placement for 3D-NoC-based multicore systems.- A constructive Heuristic for integrated mapping and TSV Placement for 3D-NoC-based multicore systems.- Discrete Particle Swarm Optimization for integrated mapping and TSV Placement for 3D-NoC-based multicore systems.- Temperature-aware application mapping strategy for 2D-NoC-based multicore systems.- Temperature-aware design strategy for 3D-NoC-based multicore systems.- Temperature-aware test strategy for 2D as well as 3D-NoC-based multicore systems.